[Intel-gfx] [PATCH 03/11] drm/i915/tgl: Add HDC Pipeline Flush

[Chris Wilson]

Quoting Mika Kuoppala (2019-10-15 16:44:41)
> Add hdc pipeline flush to ensure memory state is coherent
> in L3 when we are done.
> 
> v2: Flush also in breadcrumbs (Chris)
> 
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
> @@ -3416,7 +3417,9 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
>                                       PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
>                                       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
>                                       PIPE_CONTROL_DC_FLUSH_ENABLE |
> -                                     PIPE_CONTROL_FLUSH_ENABLE);
> +                                     PIPE_CONTROL_FLUSH_ENABLE |
> +                                     PIPE_CONTROL_HDC_PIPELINE_FLUSH);
> +

Bonus!
-Chris