[Intel-gfx] [PATCH 05/11] drm/i915/tgl: Keep FF dop clock enabled for A0

[Chris Wilson]

Quoting Mika Kuoppala (2019-10-15 16:44:43)
> To ensure correct state data for compute workloads, we
> need to keep the ff dop clock enabled.
> 
> References: HSDES#1606700617
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 ++++++++-
>  drivers/gpu/drm/i915/i915_reg.h             | 1 +
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index ba65e5018978..db7844daace9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -567,7 +567,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>                                      struct i915_wa_list *wal)
>  {
> -       /* Wa_1409142259 */
> +       /* Wa_1409142259:tgl */
>         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
>  }
> @@ -1260,6 +1260,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  {
>         struct drm_i915_private *i915 = engine->i915;
>  
> +       if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> +               /* Wa_1606700617:tgl */
> +               wa_masked_en(wal,
> +                            GEN9_CS_DEBUG_MODE1,
> +                            FF_DOP_CLOCK_GATE_DISABLE);
> +       }

Bah, and they wanted it dynamic!

> +
>         if (IS_GEN(i915, 11)) {
>                 /* This is not an Wa. Enable for better image quality */
>                 wa_masked_en(wal,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7dd126cc3ac3..781ca18cb45b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7671,6 +7671,7 @@ enum {
>  #define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1 << 10)
>  
>  #define GEN9_CS_DEBUG_MODE1            _MMIO(0x20ec)
> +  #define FF_DOP_CLOCK_GATE_DISABLE    BIT(1)

REG_BIT(1)
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris