[Intel-gfx] [PATCH 08/11] drm/i915/tgl: Wa_1409600907

[Chris Wilson]

Quoting Mika Kuoppala (2019-10-15 16:44:46)
> To avoid possible hang, we need to add depth stall if we flush the
> depth cache.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 5e98114a07a1..1ef23735c1f6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3204,6 +3204,8 @@ static int gen12_emit_flush_render(struct i915_request *request,
>                 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
>                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> +               /* Wa_1409600907:tgl */
> +               flags |= PIPE_CONTROL_DEPTH_STALL;
>                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
>                 flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
> @@ -3436,6 +3438,8 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
>                                       PIPE_CONTROL_TILE_CACHE_FLUSH |
>                                       PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
>                                       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> +                                     /* Wa_1409600907:tgl */
> +                                     PIPE_CONTROL_DEPTH_STALL |

The advice is indeed to ignore bspec and just set the bit regardless of
the programming notes.

Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris