[Intel-gfx] [PATCH] drm/i915/gt: Convert the leftover for_each_engine(gt)

[Tvrtko Ursulin]

On 18/10/2019 12:49, Chris Wilson wrote:
> Use the local gt for iterating over the available set of engines.
> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_rc6.c        | 12 ++++++------
>   drivers/gpu/drm/i915/gt/intel_ringbuffer.c |  6 +++---
>   2 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 71184aa72896..70f0e01a38b9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -65,7 +65,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>   
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> -	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   
>   	set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
> @@ -133,7 +133,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>   
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> -	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   
>   	set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
> @@ -192,7 +192,7 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6)
>   	set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> -	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   	set(uncore, GEN6_RC_SLEEP, 0);
>   	set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
> @@ -219,7 +219,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>   
> -	for_each_engine(engine, i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   
>   	set(uncore, GEN6_RC_SLEEP, 0);
> @@ -344,7 +344,7 @@ static void chv_rc6_enable(struct intel_rc6 *rc6)
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>   
> -	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   	set(uncore, GEN6_RC_SLEEP, 0);
>   
> @@ -371,7 +371,7 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>   
> -	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   
>   	set(uncore, GEN6_RC6_THRESHOLD, 0x557);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> index 311fdc0a21bc..bf631f15aa78 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> @@ -1609,7 +1609,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>   			struct intel_engine_cs *signaller;
>   
>   			*cs++ = MI_LOAD_REGISTER_IMM(num_engines);
> -			for_each_engine(signaller, i915, id) {
> +			for_each_engine(signaller, engine->gt, id) {
>   				if (signaller == engine)
>   					continue;
>   
> @@ -1663,7 +1663,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>   			i915_reg_t last_reg = {}; /* keep gcc quiet */
>   
>   			*cs++ = MI_LOAD_REGISTER_IMM(num_engines);
> -			for_each_engine(signaller, i915, id) {
> +			for_each_engine(signaller, engine->gt, id) {
>   				if (signaller == engine)
>   					continue;
>   
> @@ -1676,7 +1676,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>   			/* Insert a delay before the next switch! */
>   			*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
>   			*cs++ = i915_mmio_reg_offset(last_reg);
> -			*cs++ = intel_gt_scratch_offset(rq->engine->gt,
> +			*cs++ = intel_gt_scratch_offset(engine->gt,
>   							INTEL_GT_SCRATCH_FIELD_DEFAULT);
>   			*cs++ = MI_NOOP;
>   		}
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Regards,

Tvrtko