[Intel-gfx] [PATCH v2 1/1] drm/i915: skip the second CRC even for GEN 7 GPUs

[Harish Chegondi]

display_pipe_crc_irq_handler() skips the first CRC for all GPUs and the
second CRC for GEN8+ GPUs. The second CRC is invalid even for BYT which
is a GEN7 GPU. So, skip the second CRC even for GEN7 GPUs.

v2: Rebase

Cc: Jani Saarinen <jani.saarinen at intel.com>
Cc: Tomi Sarvela <tomi.p.sarvela at intel.com>
Cc: Petri Latvala <petri.latvala at intel.com>
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Acked-by: Jani Nikula <jani.nikula at intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi at intel.com>
References: https://bugs.freedesktop.org/show_bug.cgi?id=103191
---
 drivers/gpu/drm/i915/i915_irq.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 572a5c37cc61..312ca9d5292a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1565,11 +1565,11 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 	 * bonkers. So let's just wait for the next vblank and read
 	 * out the buggy result.
 	 *
-	 * On GEN8+ sometimes the second CRC is bonkers as well, so
+	 * On GEN7+ sometimes the second CRC is bonkers as well, so
 	 * don't trust that one either.
 	 */
 	if (pipe_crc->skipped <= 0 ||
-	    (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
+	    (INTEL_GEN(dev_priv) >= 7 && pipe_crc->skipped == 1)) {
 		pipe_crc->skipped++;
 		spin_unlock(&pipe_crc->lock);
 		return;
-- 
2.21.0