[Intel-gfx] [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT

[Mika Kuoppala]

Tapani Pälli <tapani.palli at intel.com> writes:

> As with commit 3fe0107e45ab, this change fixes multiple tests that are
> using the invocation counts. Documentation doesn't list the workaround
> for TGL but applying it fixes the tests.
>
> Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index af8a8183154a..86ded203b2dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>  
>  static void tgl_whitelist_build(struct intel_engine_cs *engine)
>  {
> +	struct i915_wa_list *w = &engine->whitelist;
> +
> +	switch (engine->class) {
> +	case RENDER_CLASS:
> +		/*
> +		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl

Tried to find info about this but failed.

> +		 *
> +		 * This covers 4 registers which are next to one another :
> +		 *   - PS_INVOCATION_COUNT
> +		 *   - PS_INVOCATION_COUNT_UDW
> +		 *   - PS_DEPTH_COUNT
> +		 *   - PS_DEPTH_COUNT_UDW
> +		 */
> +		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> +				  RING_FORCE_TO_NONPRIV_ACCESS_RD |
> +				  RING_FORCE_TO_NONPRIV_RANGE_4);

The register spec is identical with gen11 so ok to whitelist.

Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

> +		break;
> +	default:
> +		break;
> +	}
>  }
>  
>  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> -- 
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx