[Intel-gfx] [PATCH] drm/i915/tc: Clear DKL_TX_PMD_LANE_SUS before program voltage swing

[Lucas De Marchi]

On Mon, Oct 21, 2019 at 03:34:08PM -0700, Jose Souza wrote:
>This sequence was recently added to fix internal HW sequences to
>reset TC ports.
>
>HSDES: 1507287614
>HSDES: 14010071447
>BSpec: 49292
>Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza at intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
> drivers/gpu/drm/i915/i915_reg.h          | 6 ++++++
> 2 files changed, 8 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 9ba794cb9b4f..74cfdd8dfec4 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -2838,6 +2838,8 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
> 	for (ln = 0; ln < 2; ln++) {
> 		I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
>
>+		I915_WRITE(DKL_TX_PMD_LANE_SUS(tc_port), 0);
>+
> 		/* All the registers are RMW */
> 		val = I915_READ(DKL_TX_DPCNTL0(tc_port));
> 		val &= ~dpcnt_mask;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 855db888516c..767891c0332b 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10249,6 +10249,12 @@ enum skl_power_gate {
> 						     _DKL_PHY2_BASE) + \
> 						     _DKL_TX_FW_CALIB)
>
>+#define _DKL_TX_PMD_LANE_SUS				0xD00
>+#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
>+							  _DKL_PHY1_BASE, \
>+							  _DKL_PHY2_BASE) + \
>+							  _DKL_TX_PMD_LANE_SUS)
>+
> #define _DKL_TX_DW17					0xDC4
> #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
> 						     _DKL_PHY1_BASE, \
>-- 
>2.23.0
>
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