[Intel-gfx] [PATCH] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency

[Matthew Auld]

On Fri, 25 Oct 2019 at 22:06, Chris Wilson <chris at chris-wilson.co.uk> wrote:
>
> Currently we insert a arbitration point every 128MiB during a blitter
> copy. At 8GiB/s, this is around 30ms. This is a little on the large side
> if we need to inject a high priority work, so reduced it down to 8MiB or
> roughly 1ms.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld at intel.com>
> ---
> Ok, I need to do a selftest to ensure we are exceeding the estimated
> blitter throughtput, and I would also like a test to measure the
> preemption latency directly. Remind me!
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> index 516e61e99212..7e25f05939bc 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> @@ -17,7 +17,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
>                                          u32 value)
>  {
>         struct drm_i915_private *i915 = ce->vm->i915;
> -       const u32 block_size = S16_MAX * PAGE_SIZE;
> +       const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */

Also update the copy?

Not sure if this will need more tuning.
Reviewed-by: Matthew Auld <matthew.auld at intel.com>