[Intel-gfx] [PATCH v9 0/2] Refactor Gen11+ SAGV support

[Stanislav Lisovskiy]

For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.

Stanislav Lisovskiy (2):
  drm/i915: Refactor intel_can_enable_sagv
  drm/i915: Restrict qgv points which don't have enough bandwidth.

 drivers/gpu/drm/i915/display/intel_atomic.c   |  16 +
 drivers/gpu/drm/i915/display/intel_atomic.h   |   3 +
 drivers/gpu/drm/i915/display/intel_bw.c       | 111 +++++--
 drivers/gpu/drm/i915/display/intel_bw.h       |   2 +
 drivers/gpu/drm/i915/display/intel_display.c  |  63 +++-
 .../drm/i915/display/intel_display_types.h    |  12 +
 drivers/gpu/drm/i915/i915_drv.h               |   8 +
 drivers/gpu/drm/i915/i915_reg.h               |   5 +
 drivers/gpu/drm/i915/intel_pm.c               | 299 +++++++++++++++++-
 drivers/gpu/drm/i915/intel_sideband.c         |  27 +-
 10 files changed, 504 insertions(+), 42 deletions(-)

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2.17.1