[Intel-gfx] [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture

[Daniele Ceraolo Spurio]

On 10/29/19 2:44 PM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2019-10-29 21:23:16)
>>
>>
>> On 10/29/19 2:58 AM, Matthew Auld wrote:
>>> From: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
>>>
>>> We can't fence anything without aperture.
>>>
>>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
>>> Signed-off-by: Stuart Summers <stuart.summers at intel.com>
>>> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++++--
>>>    1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> index 321189e1b0f2..71efccfde122 100644
>>> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> @@ -846,8 +846,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
>>>    
>>>        detect_bit_6_swizzle(ggtt);
>>>    
>>> -     if (INTEL_GEN(i915) >= 7 &&
>>> -         !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
>>> +     if (!i915_ggtt_has_aperture(ggtt))
>>
>> Daniel had mentioned that the fencing HW has been nerfed in gen12 and
>> suggested settings num_fences to zero for all gen12+. Should we go
>> directly with that?
> 
> Do fences exist, yes/no? If there are literally no fences forevermore...
> tgl begs to differ though.
> -Chris
> 

The registers are there in the specs and I don't see any special notes 
about their usage. I'll leave it to Daniel to comment on the capability 
reduction he mentioned. Not a blocker for this patch in the meantime.

Daniele