[Intel-gfx] [PATCH v21 06/10] drm/i915: Add proper SAGV support for TGL+
Stanislav Lisovskiy
stanislav.lisovskiy at intel.com
Fri Apr 3 06:29:10 UTC 2020
Let's refactor the whole SAGV logic, moving
the main calculations from intel_can_enable_sagv
to intel_compute_sagv_mask, which also handles
this in a unified way calling gen specific
functions to evaluate if SAGV is allowed for
each crtc. If crtc sagv mask have been changed
we serialize access and modify global state.
intel_can_enable_sagv now uses bw_state which
stores all information related to SAGV and
is now a trivial helper.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
v5: - Added SAGV global state to dev_priv, because
we need to track all pipes, not only those
in atomic state. Each pipe has now correspondent
bit mask reflecting, whether it can tolerate
SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
usage check.
v6: - Fixed rebase conflicts
v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
calls when copying level 0 water marks for enabled SAGV, to
fix this now simply using that field right away, without copying,
for that introduced a new wm_level accessor which decides which
wm_level to return based on SAGV state.
v8: - Protect crtc_sagv_mask same way as we do for other global state
changes: i.e check if changes are needed, then grab all crtc locks
to serialize the changes(Ville Syrjälä)
- Add crtc_sagv_mask caching in order to avoid needless recalculations
(Matthew Roper)
- Put back Gen12 SAGV switch in order to get it enabled in separate
patch(Matthew Roper)
- Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
- Check if there are no active pipes in intel_can_enable_sagv
instead of platform specific functions(Matthew Roper), same
for intel_has_sagv check.
v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
- crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
- Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
- Extracted skl_plane_wm_level function and passing latency to
separate patches(Ville Syrjälä)
- Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
(Ville Syrjälä)
- Now using simple assignment for sagv_wm0 as it contains only
pod types and no pointers(Ville Syrjälä)
- Fixed intel_can_enable_sagv not to do double duty, now it only
check SAGV bits by ANDing those between local and global state.
The SAGV masks are now computed after watermarks are available,
in order to be able to figure out if ddb ranges are fitting nicely.
(Ville Syrjälä)
- Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
when using skl_plane_wm_level accessor, as we had previously for
Gen11+ color plane and regular wm levels, so probably both
has to be recalculated with additional SAGV block time for Level 0.
v10: - Starting to use new global state for storing pipe_sagv_mask
v11: - Fixed rebase conflict with recent drm-tip
- Check if we really need to recalculate SAGV mask, otherwise
bail out without making any changes.
- Use cached SAGV result, instead of recalculating it everytime,
if bw_state hasn't changed.
v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
if we don't recalculated watermarks, bw_state is not recalculated,
thus leading to SAGV state not recalculated by the commit state,
which is still calling intel_can_enable_sagv function. Fix that
by just analyzing the current global bw_state object - because
we simply have no other objects related to that.
v13: - Rebased, fixed warnings regarding long lines
- Changed function call sites from intel_atomic_bw* to
intel_wb_* as was suggested.(Jani Nikula)
- Taken ddb_state_changed and bw_state_changed into use.
v14: - total_affected_planes is no longer needed to check for ddb changes,
just as active_pipe_changes.
v15: - Fixed stupid mistake with uninitialized crtc in
skl_compute_sagv_mask.
v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted
flag to indicate SAGV readiness for the pipe(Ville Syrjälä)
- Added return value to intel_compute_sagv_mask which call
intel_atomic_serialize_global_state in order to properly
propagate EDEADLCK to drm.
- Based on the discussion with Ville, removed active_pipe_changes
check and also there seems to be no need for checking
ddb_state_changes as well.
Instead we just iterate through crtcs in state - having
crtc in a state already guarantees that it is at least read-locked
Having additional flag to check if there actually were some plane
wm/ddb changes would be probably added later as an optimization.
- We can't get parent atomic state from crtc_state at commit stage
(nice drm feature), also propagating state through function call
chain seems to be overkill and not possible(cursor legacy updates)
Querying for bw_state object from global state is not possible as
it might get swapped with other global state.
So... just sticked can_sagv boolean into wm crtc state.
v17: - Skip inactive crtcs, when checking for SAGV-readiness.
v18: - Switch to use intel_atomic_crtc_state_for_each_plane_state
instead of for_each_intel_plane_on_crtc and fixed previous
code, which was using old plane state, which caused NULL ptr
dereference, bacause that code is now called before we swap the
state.
v19: - Use intel_atomic_bw_* pattern again
- Optimized sagv checks in verify_wm_state(Ville Syrjälä)
- Do intel_compute_sagv_mask after ddb is allocated(Ville Syrjälä),
using it's results
- Use bw_state in intel_can_enable_sagv
- Use COLOR_PLANE enum instead of boolean yuv or "0", "1" magic
- Extracted sagv wm0 calculation into separate skl_compute_sagv_wm
function(Ville Syrjälä)
v20: - Added check for NULL for bw_state in commit_tail
- Removed long comments and warns(Ville)
- Extracted if ladder from compute_sagv(Ville)
- Removed some debugs(Ville)
- Extracted sagv_wm0 init from the loop in skl_pipe_wm_get_hw_state
(Ville)
- Now printing sagv_wm0 separately(Ville)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
Cc: Ville Syrjälä <ville.syrjala at intel.com>
Cc: James Ausmus <james.ausmus at intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 6 +
drivers/gpu/drm/i915/display/intel_display.c | 28 ++-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 179 ++++++++++++++++--
drivers/gpu/drm/i915/intel_pm.h | 4 +-
5 files changed, 196 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index ac004d6f4276..d6df91058223 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,12 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+ * Contains a bit mask, used to determine, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u8 pipe_sagv_reject;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e630429af2c0..a601177b21ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14009,7 +14009,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0)))
continue;
drm_err(&dev_priv->drm,
@@ -14064,7 +14066,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0)))
continue;
drm_err(&dev_priv->drm,
@@ -15535,6 +15539,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
crtc->config = new_crtc_state;
if (state->modeset) {
+
drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
intel_set_cdclk_pre_plane_update(state);
@@ -15543,8 +15548,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ const struct intel_bw_state *bw_state =
+ intel_atomic_get_new_bw_state(state);
+
+ if (bw_state && !intel_can_enable_sagv(bw_state))
+ intel_disable_sagv(dev_priv);
+ }
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -15644,8 +15654,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ struct intel_bw_state *bw_state;
+
+ bw_state = intel_atomic_get_new_bw_state(state);
+
+ if (bw_state && state->modeset && intel_can_enable_sagv(bw_state))
+ intel_enable_sagv(dev_priv);
+ }
drm_atomic_helper_commit_hw_done(&state->base);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 523e0444b373..51fa5a746a5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -679,6 +679,8 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
@@ -689,6 +691,7 @@ enum color_plane {
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
+ bool can_sagv;
};
enum vlv_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27d4d626cb34..994c6dc0fa4f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
/* HACK! */
@@ -3824,29 +3825,88 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
return icl_crtc_can_enable_sagv(crtc_state);
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
+
+bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
+{
+ return bw_state->pipe_sagv_reject == 0;
+}
+
+bool intel_can_enable_sagv_on_pipe(const struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
+ bool res;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ res = tgl_crtc_can_enable_sagv(new_crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 11)
+ res = icl_crtc_can_enable_sagv(new_crtc_state);
+ else
+ res = skl_crtc_can_enable_sagv(new_crtc_state);
+
+ return res;
+}
+
+static int intel_compute_sagv_mask(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *crtc_state;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_bw_state *new_bw_state = NULL;
+ const struct intel_bw_state *old_bw_state = NULL;
int i;
+ bool can_sagv;
if (!intel_has_sagv(dev_priv))
- return false;
+ return 0;
- for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- bool can_sagv;
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
- if (INTEL_GEN(dev_priv) >= 11)
- can_sagv = icl_crtc_can_enable_sagv(crtc_state);
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+
+ if (intel_can_enable_sagv_on_pipe(new_crtc_state))
+ new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
else
- can_sagv = skl_crtc_can_enable_sagv(crtc_state);
+ new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
+ }
- if (!can_sagv)
- return false;
+ if (!new_bw_state || !old_bw_state)
+ return 0;
+
+ can_sagv = new_bw_state->pipe_sagv_reject == 0;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
+
+ /*
+ * Due to drm limitation at commit state, when
+ * changes are written the whole atomic state is
+ * zeroed away => which prevents from using it,
+ * so just sticking it into pipe wm state for
+ * keeping it simple - anyway this is related to wm.
+ * Proper way in ideal universe would be of course not
+ * to lose parent atomic state object from child crtc_state,
+ * and stick to OOP programming principles, which had been
+ * scientifically proven to work.
+ */
+ pipe_wm->can_sagv = can_sagv;
}
- return true;
+ if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
/*
@@ -4579,12 +4639,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
int level,
enum color_plane color_plane)
{
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+ if (!level) {
+ if (pipe_wm->can_sagv)
+ return color_plane == COLOR_PLANE_Y ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
+ }
return color_plane == COLOR_PLANE_Y ? &wm->wm[level] : &wm->uv_wm[level];
}
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum plane_id plane_id;
+
+ if (!crtc_state->hw.active)
+ return true;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_ddb_entry *plane_alloc =
+ &crtc_state->wm.skl.plane_ddb_y[plane_id];
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
+ return false;
+ }
+
+ return true;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -5166,10 +5253,17 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ enum color_plane color_plane)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = color_plane == COLOR_PLANE_UV ?
+ plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
for (level = 0; level <= max_level; level++) {
@@ -5183,6 +5277,40 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
}
}
+static void skl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
+ const struct skl_wm_params *wm_params,
+ struct skl_plane_wm *plane_wm,
+ enum color_plane color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct skl_wm_level *sagv_wm = color_plane == COLOR_PLANE_UV ?
+ &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
+ struct skl_wm_level *levels = color_plane == COLOR_PLANE_UV ?
+ plane_wm->uv_wm : plane_wm->wm;
+
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ sagv_wm);
+ DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+ sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+ } else {
+ /* Since all members are POD */
+ *sagv_wm = levels[0];
+ }
+}
+
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wp,
struct skl_plane_wm *wm)
@@ -5263,7 +5391,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, COLOR_PLANE_Y);
+ skl_compute_sagv_wm(crtc_state, &wm_params, wm, COLOR_PLANE_Y);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -5285,7 +5414,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, COLOR_PLANE_UV);
+ skl_compute_sagv_wm(crtc_state, &wm_params, wm, COLOR_PLANE_UV);
return 0;
}
@@ -5699,6 +5829,14 @@ skl_print_wm_changes(struct intel_atomic_state *state)
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
new_wm->trans_wm.min_ddb_alloc);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 min ddb %4d blocks %4d lines %4d\n"
+ "-> min_ddb %4d blocks %4d lines %4d\n",
+ plane->base.base.id, plane->base.name, old_wm->sagv_wm0.min_ddb_alloc,
+ old_wm->sagv_wm0.plane_res_b, old_wm->sagv_wm0.plane_res_l,
+ new_wm->sagv_wm0.min_ddb_alloc, new_wm->sagv_wm0.plane_res_b,
+ new_wm->sagv_wm0.plane_res_l);
}
}
}
@@ -5859,6 +5997,10 @@ skl_compute_wm(struct intel_atomic_state *state)
if (ret)
return ret;
+ ret = intel_compute_sagv_mask(state);
+ if (ret)
+ return ret;
+
/*
* skl_compute_ddb() will have adjusted the final watermarks
* based on how much ddb is available. Now we can actually
@@ -5988,6 +6130,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
skl_wm_level_from_reg_val(val, &wm->wm[level]);
}
+ memcpy(&wm->sagv_wm0, &wm->wm[0],
+ sizeof(struct skl_wm_level));
+
if (plane_id != PLANE_CURSOR)
val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
else
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..e41637b3a05d 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -9,6 +9,7 @@
#include <linux/types.h>
#include "i915_reg.h"
+#include "display/intel_bw.h"
struct drm_device;
struct drm_i915_private;
@@ -41,7 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
+bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
--
2.24.1.485.gad05a3d8e5
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