[Intel-gfx] [PATCH v22 00/13] SAGV support for Gen12+

[Stanislav Lisovskiy]

For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.

Stanislav Lisovskiy (13):
  drm/i915: Start passing latency as parameter
  drm/i915: Eliminate magic numbers "0" and "1" from color plane
  drm/i915: Introduce skl_plane_wm_level accessor.
  drm/i915: Add intel_atomic_get_bw_*_state helpers
  drm/i915: Prepare to extract gen specific functions from
    intel_can_enable_sagv
  drm/i915: Add pre/post plane updates for SAGV
  drm/i915: Use bw state for per crtc SAGV evaluation
  drm/i915: Separate icl and skl SAGV checking
  drm/i915: Add TGL+ SAGV support
  drm/i915: Added required new PCode commands
  drm/i915: Rename bw_state to new_bw_state
  drm/i915: Restrict qgv points which don't have enough bandwidth.
  drm/i915: Enable SAGV support for Gen12

 drivers/gpu/drm/i915/display/intel_bw.c       | 191 +++++--
 drivers/gpu/drm/i915/display/intel_bw.h       |  24 +
 drivers/gpu/drm/i915/display/intel_display.c  |  21 +-
 .../drm/i915/display/intel_display_types.h    |  11 +
 drivers/gpu/drm/i915/i915_reg.h               |   5 +
 drivers/gpu/drm/i915/intel_pm.c               | 476 +++++++++++++++---
 drivers/gpu/drm/i915/intel_pm.h               |   8 +-
 drivers/gpu/drm/i915/intel_sideband.c         |   2 +
 8 files changed, 604 insertions(+), 134 deletions(-)

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2.24.1.485.gad05a3d8e5