[Intel-gfx] [PATCH] agp/intel: Reinforce the barrier after GTT updates

[Andi Shyti]

Hi Chris,

> After changing the timing between GTT updates and execution on the GPU,
> we started seeing sporadic failures on Ironlake. These were narrowed
> down to being an insufficiently strong enough barrier/delay after
> updating the GTT and scheduling execution on the GPU. By forcing the
> uncached read, and adding the missing barrier for the singular
> insert_page (relocation paths), the sporadic failures go away.
> 
> Fixes: 983d308cb8f6 ("agp/intel: Serialise after GTT updates")
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: stable at vger.kernel.org # v4.0+

Acked-by: Andi Shyti <andi.shyti at intel.com>

Andi

> ---
>  drivers/char/agp/intel-gtt.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 66a62d17a3f5..3d42fc4290bc 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -846,6 +846,7 @@ void intel_gtt_insert_page(dma_addr_t addr,
>  			   unsigned int flags)
>  {
>  	intel_private.driver->write_entry(addr, pg, flags);
> +	readl(intel_private.gtt + pg);
>  	if (intel_private.driver->chipset_flush)
>  		intel_private.driver->chipset_flush();
>  }
> @@ -871,7 +872,7 @@ void intel_gtt_insert_sg_entries(struct sg_table *st,
>  			j++;
>  		}
>  	}
> -	wmb();
> +	readl(intel_private.gtt + j - 1);
>  	if (intel_private.driver->chipset_flush)
>  		intel_private.driver->chipset_flush();
>  }
> @@ -1105,6 +1106,7 @@ static void i9xx_cleanup(void)
>  
>  static void i9xx_chipset_flush(void)
>  {
> +	wmb();
>  	if (intel_private.i9xx_flush_page)
>  		writel(1, intel_private.i9xx_flush_page);
>  }