[Intel-gfx] [PATCH] drm/edid: Fix off-by-one in DispID DTD pixel clock

[Manasi Navare]

On Thu, Apr 23, 2020 at 06:17:43PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> The DispID DTD pixel clock is documented as:
> "00 00 00 h → FF FF FF h | Pixel clock ÷ 10,000 0.01 → 167,772.16 Mega Pixels per Sec"
> Which seems to imply that we to add one to the raw value.
> 
> Reality seems to agree as there are tiled displays in the wild
> which currently show a 10kHz difference in the pixel clock
> between the tiles (one tile gets its mode from the base EDID,
> the other from the DispID block).
> 
> Cc: stable at vger.kernel.org
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/27
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Makes total sense,

Reviewed-by: Manasi Navare <manasi.d.navare at intel.com>

Manasi

> ---
>  drivers/gpu/drm/drm_edid.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 43b6ca364daa..544d2603f5fc 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5120,7 +5120,7 @@ static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *d
>  	struct drm_display_mode *mode;
>  	unsigned pixel_clock = (timings->pixel_clock[0] |
>  				(timings->pixel_clock[1] << 8) |
> -				(timings->pixel_clock[2] << 16));
> +				(timings->pixel_clock[2] << 16)) + 1;
>  	unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
>  	unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
>  	unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
> -- 
> 2.24.1
> 
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