[Intel-gfx] [PATCH 7/9] drm/i915/gen12: Wait on previous flush on invalidate

[Mika Kuoppala]

Flush enable bit is a sync point which makes this
pipecontrol to wait that everything on a previous
pipe control are flushed. Enable it to make
sure that our invalidates doesn't overlap.

Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7807f53eae18..789efece1fc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4590,6 +4590,8 @@ static int gen12_emit_flush_render(struct i915_request *request,
 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 
+		flags |= PIPE_CONTROL_FLUSH_ENABLE;
+
 		flags |= PIPE_CONTROL_STORE_DATA_INDEX;
 		flags |= PIPE_CONTROL_QW_WRITE;
 
-- 
2.17.1