[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

[Chris Wilson]

Quoting Patchwork (2020-04-30 17:25:55)
> == Series Details ==
> 
> Series: series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"
> URL   : https://patchwork.freedesktop.org/series/76777/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_8401 -> Patchwork_17529
> ====================================================
> 
> Summary
> -------
> 
>   **SUCCESS**

Coherency/pipecontrol are the worst. How do we design tests to even
detect and probe for unknown missed flushes?

I wonder if there are some debug [context] registers that can tell us the
status of all caches? Set to nonzero for a dirty cache, and we're allowed
to set, but is then cleared by pipecontrol. Seems worth asking.
-Chris