[Intel-gfx] [PATCH v3 2/2] drm/i915/display: Implement WA 1408330847

[Mun, Gwan-gyeong]

On Mon, 2020-07-06 at 16:43 -0700, José Roberto de Souza wrote:
> From the 3 WAs for PSR2 man track/selective fetch this is only one
> needed when doing single full frames at every flip.
> 
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 19 +++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h          |  1 +
>  2 files changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index d30a3560b794..2b004ee9619c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -553,13 +553,21 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
>  		val |= EDP_PSR2_FAST_WAKE(7);
>  	}
>  
> -	if (dev_priv->psr.psr2_sel_fetch_enabled)
> +	if (dev_priv->psr.psr2_sel_fetch_enabled) {
> +		/* WA 1408330847 */
> +		if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)
> ||
> +		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> +			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> +				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> +				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> +
>  		intel_de_write(dev_priv,
>  			       PSR2_MAN_TRK_CTL(dev_priv-
> >psr.transcoder),
>  			       PSR2_MAN_TRK_CTL_ENABLE);
> -	else if (HAS_PSR2_SEL_FETCH(dev_priv))
> +	} else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
>  		intel_de_write(dev_priv,
>  			       PSR2_MAN_TRK_CTL(dev_priv-
> >psr.transcoder), 0);
> +	}
>  
>  	/*
>  	 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec
> is
> @@ -1099,6 +1107,13 @@ static void intel_psr_disable_locked(struct
> intel_dp *intel_dp)
>  				    psr_status_mask, 2000))
>  		drm_err(&dev_priv->drm, "Timed out waiting PSR idle
> state\n");
>  
> +	/* WA 1408330847 */
> +	if (dev_priv->psr.psr2_sel_fetch_enabled &&
> +	    (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> +	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> +		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> +			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> +
>  	/* Disable PSR on Sink */
>  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 5bee4e212866..d29a8cc776d3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7857,6 +7857,7 @@ enum {
>  # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
>  
>  #define CHICKEN_PAR1_1			_MMIO(0x42080)
> +#define  DIS_RAM_BYPASS_PSR2_MAN_TRACK	(1 << 16)
>  #define  SKL_DE_COMPRESSED_HASH_MODE	(1 << 15)
>  #define  DPA_MASK_VBLANK_SRD		(1 << 15)
>  #define  FORCE_ARB_IDLE_PLANES		(1 << 14)
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>