[Intel-gfx] [PATCH v5 3/5] drm/i915: Introduce scaling filter related registers and bit fields.

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces at lists.freedesktop.org> On Behalf Of Pankaj
> Bharadiya
> Sent: Monday, August 3, 2020 10:00 AM
> To: jani.nikula at linux.intel.com; daniel at ffwll.ch; intel-gfx at lists.freedesktop.org;
> dri-devel at lists.freedesktop.org; ville.syrjala at linux.intel.com;
> daniels at collabora.com; Lattannavar, Sameer <sameer.lattannavar at intel.com>;
> Joonas Lahtinen <joonas.lahtinen at linux.intel.com>; Vivi, Rodrigo
> <rodrigo.vivi at intel.com>; David Airlie <airlied at linux.ie>
> Cc: Laxminarayan Bharadiya, Pankaj
> <pankaj.laxminarayan.bharadiya at intel.com>
> Subject: [PATCH v5 3/5] drm/i915: Introduce scaling filter related registers and bit
> fields.

You can drop the "." from header.

Overall Changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar at intel.com>

> Introduce scaler registers and bit fields needed to configure the scaling filter in
> prgrammed mode and configure scaling filter coefficients.
> 
> changes since v3:
> * None
> changes since v2:
> * Change macro names to CNL_* and  use +(set)*8 instead of adding
>   another trip through _PICK_EVEN (Ville).
> changes since v1:
> * None
> changes since RFC:
> * Parametrize scaler coeffient macros by 'set' (Ville)
> 
> Signed-off-by: Shashank Sharma <shashank.sharma at intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
> Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5eae593ee784..e582021cc208 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7391,6 +7391,7 @@ enum {
>  #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
>  #define PS_FILTER_MASK         (3 << 23)
>  #define PS_FILTER_MEDIUM       (0 << 23)
> +#define PS_FILTER_PROGRAMMED   (1 << 23)
>  #define PS_FILTER_EDGE_ENHANCE (2 << 23)
>  #define PS_FILTER_BILINEAR     (3 << 23)
>  #define PS_VERT3TAP            (1 << 21)
> @@ -7405,6 +7406,10 @@ enum {
>  #define PS_VADAPT_MODE_MOST_ADAPT  (3 << 5)  #define
> PS_PLANE_Y_SEL_MASK  (7 << 5)  #define PS_PLANE_Y_SEL(plane) (((plane) + 1)
> << 5)
> +#define PS_Y_VERT_FILTER_SELECT(set)   ((set) << 4)
> +#define PS_Y_HORZ_FILTER_SELECT(set)   ((set) << 3)
> +#define PS_UV_VERT_FILTER_SELECT(set)  ((set) << 2) #define
> +PS_UV_HORZ_FILTER_SELECT(set)  ((set) << 1)
> 
>  #define _PS_PWR_GATE_1A     0x68160
>  #define _PS_PWR_GATE_2A     0x68260
> @@ -7467,6 +7472,17 @@ enum {
>  #define _PS_ECC_STAT_2B     0x68AD0
>  #define _PS_ECC_STAT_1C     0x691D0
> 
> +#define _PS_COEF_SET0_INDEX_1A	   0x68198
> +#define _PS_COEF_SET0_INDEX_2A	   0x68298
> +#define _PS_COEF_SET0_INDEX_1B	   0x68998
> +#define _PS_COEF_SET0_INDEX_2B	   0x68A98
> +#define PS_COEE_INDEX_AUTO_INC	   (1 << 10)
> +
> +#define _PS_COEF_SET0_DATA_1A	   0x6819C
> +#define _PS_COEF_SET0_DATA_2A	   0x6829C
> +#define _PS_COEF_SET0_DATA_1B	   0x6899C
> +#define _PS_COEF_SET0_DATA_2B	   0x68A9C
> +
>  #define _ID(id, a, b) _PICK_EVEN(id, a, b)
>  #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe,        \
>  			_ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
> @@ -7495,7 +7511,13 @@ enum {
>  #define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe,     \
>  			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
>  			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
> +#define CNL_PS_COEF_INDEX_SET(pipe, id, set)  _MMIO_PIPE(pipe,    \
> +			_ID(id, _PS_COEF_SET0_INDEX_1A,
> _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
> +			_ID(id, _PS_COEF_SET0_INDEX_1B,
> _PS_COEF_SET0_INDEX_2B) + (set) * 8)
> 
> +#define CNL_PS_COEF_DATA_SET(pipe, id, set)  _MMIO_PIPE(pipe,     \
> +			_ID(id, _PS_COEF_SET0_DATA_1A,
> _PS_COEF_SET0_DATA_2A) + (set) * 8, \
> +			_ID(id, _PS_COEF_SET0_DATA_1B,
> _PS_COEF_SET0_DATA_2B) + (set) * 8)
>  /* legacy palette */
>  #define _LGC_PALETTE_A           0x4a000
>  #define _LGC_PALETTE_B           0x4a800
> --
> 2.23.0
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel