[Intel-gfx] [PATCH] drm/i915/dp: DPTX writes Swing/Pre-emphs(DPCD 0x103-0x106) requested during PHY Layer testing.

[Navare, Manasi]

On Fri, Aug 21, 2020 at 11:48:37PM -0700, Khaled Almahallawy wrote:
> Source needs to write DPCD 103-106 after receiving a PHY request to change
> swing/pre-emphasis after reading DPCD 206-207. This is especially needed if
> there is a retimer between source and sink and the retimer implements AUX_CH
> interception scheme to manage DP PHY settings (e.g. adjusting Swing/Pre-emphasis
> equalization level) for DP output channel . If the source doesn't write to
> DPCD 103-106, the retimer may not output the requested swing/pre-emphasis and
> eventually we fail compliance.
> 
> Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 79c27f91f42c..5044201ca742 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5503,6 +5503,9 @@ void intel_dp_process_phy_request(struct intel_dp *intel_dp)
>  
>  	intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
>  
> +	drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
> +				intel_dp->train_set, intel_dp->lane_count);

Does this also help with spitting out the correct voltage levels during the actual training
Does this fix LT failure seen on Type C ports with retimers?

Manasi

> +
>  	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
>  				    link_status[DP_DPCD_REV]);
>  }
> -- 
> 2.17.1
>