[Intel-gfx] [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Souza, Jose]

On Tue, 2020-12-01 at 07:51 -0800, José Roberto de Souza wrote:
> On Tue, 2020-12-01 at 20:00 +0530, Uma Shankar wrote:
> > There are some corner cases wrt underrun when we enable
> > FBC with PSR2 on TGL. Recommendation from hardware is to
> > keep this combination disabled.
> > 
> > Bspec: 50422 HSD: 14010260002
> > 
> > v2: Added psr2 enabled check from crtc_state (Anshuman)
> > Added Bspec link and HSD referneces (Jose)
> > 
> > v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
> > and removed the crtc->config usages, as per Ville's recommendation.
> > 
> > v4: Introduced a variable in fbc state_cache instead of the earlier
> > plane.visible WA, as suggested by Jose.
> > 
> > Signed-off-by: Uma Shankar <uma.shankar at intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 29 ++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/i915_drv.h          |  1 +
> >  2 files changed, 30 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index a5b072816a7b..ff2f2c00a10e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -700,7 +700,21 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> >  	struct intel_fbc_state_cache *cache = &fbc->state_cache;
> >  	struct drm_framebuffer *fb = plane_state->hw.fb;
> >  
> > 
> > 
> > 
> > +	if (crtc_state->has_psr2)
> > +		cache->psr2_active = true;
> > +	else
> > +		cache->psr2_active = false;
> 
> cache->psr2_active = crtc_state->has_psr2;
> 
> 
> > +
> > +	/*
> > +	 * Tigerlake is not supporting FBC with PSR2.
> > +	 * Recommendation is to keep this combination disabled
> > +	 * Bspec: 50422 HSD: 14010260002
> > +	 */
> > +	if (IS_TIGERLAKE(dev_priv) && cache->psr2_active)
> > +		return;
> 
> 
> Here you should only set psr2_active, add it to the bottom of intel_fbc_update_state_cache.
> The check should only be done in intel_fbc_can_activate().
> 
> > +
> >  	cache->plane.visible = plane_state->uapi.visible;
> > +
> >  	if (!cache->plane.visible)
> >  		return;
> >  
> > 
> > 
> > 
> > 
> > 
> > 
> > 
> > @@ -799,6 +813,16 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> >  	struct intel_fbc *fbc = &dev_priv->fbc;
> >  	struct intel_fbc_state_cache *cache = &fbc->state_cache;
> >  
> > 
> > 
> > 
> > 
> > 
> > 
> > 
> > +	/*
> > +	 * Tigerlake is not supporting FBC with PSR2.
> > +	 * Recommendation is to keep this combination disabled
> > +	 * Bspec: 50422 HSD: 14010260002
> > +	 */
> > +	if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
> > +		fbc->no_fbc_reason = "not supported with PSR2";
> > +		return false;
> > +	}
> > +
> >  	if (!intel_fbc_can_enable(dev_priv))
> >  		return false;
> >  
> > 
> > 
> > 
> > 
> > 
> > 
> > 
> > @@ -1273,6 +1297,11 @@ void intel_fbc_enable(struct intel_atomic_state *state,
> >  	if (!cache->plane.visible)
> >  		goto out;
> >  
> > 
> > 
> > 
> > 
> > 
> > 
> > 
> > +	if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
> > +		fbc->no_fbc_reason = "not supported with PSR2";
> > +		goto out;
> > +	}

Also no need to check it here, only in intel_fbc_can_activate.
We already allocate the cfb even when other reasons do not allow FBC to be activated.

> > +
> >  	if (intel_fbc_alloc_cfb(dev_priv,
> >  				intel_fbc_calculate_cfb_size(dev_priv, cache),
> >  				plane_state->hw.fb->format->cpp[0])) {
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 15be8debae54..f4e08c1a5867 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -416,6 +416,7 @@ struct intel_fbc {
> >  		u16 gen9_wa_cfb_stride;
> >  		u16 interval;
> >  		s8 fence_id;
> > +		bool psr2_active;
> >  	} state_cache;
> >  
> > 
> > 
> > 
> > 
> > 
> > 
> > 
> >  	/*
>