[Intel-gfx] [PATCH 1/3] drm/i915/gt: stop ignoring read with wa_masked_field_set

[Chris Wilson]

Quoting Lucas De Marchi (2020-12-09 04:52:44)
> When using masked registers, there is nothing to clear since a masked
> register has the mask in the upper 16b: we can just write to the
> location we want and use the mask to control what bits we are writing
> to.
> 
> However that doesn't mean we don't want to read back the register and
> check the value actually matched what we wanted to write, i.e. that
> the WA stick. That should be an explicit opt-out for registers that are
> either write-only or that are affected by hardware misbehavior.
> 
> Moreover both wa_masked_en() and wa_masked_dis() check the WA stick, so
> skipping the check just because the field is more than 1 bit is
> surprising and error-prone.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 2db1e68d7464..70d4ca2776a3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -233,7 +233,7 @@ static void
>  wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
>                     u32 mask, u32 val)
>  {
> -       wa_write_masked_or(wal, reg, 0, _MASKED_FIELD(mask, val));
> +       wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask);

Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris