[Intel-gfx] [PATCH] drm/i915/gt: Rearrange snb workarounds

[Chris Wilson]

Quoting Mika Kuoppala (2020-12-10 10:36:07)
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> 
> > Some rcs0 workarounds were being incorrectly applied to the GT, and so
> > we failed to restore the expected register settings after a reset.
> >
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 67 ++++++++++-----------
> >  1 file changed, 33 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index b5339a36d256..50cfe82f18a9 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -823,40 +823,6 @@ ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> >  static void
> >  snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> >  {
> > -     /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
> > -     wa_masked_en(wal,
> > -                  _3D_CHICKEN,
> > -                  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
> > -
> > -     /* WaDisable_RenderCache_OperationalFlush:snb */
> > -     wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
> > -
> > -     /*
> > -      * BSpec recommends 8x4 when MSAA is used,
> > -      * however in practice 16x4 seems fastest.
> > -      *
> > -      * Note that PS/WM thread counts depend on the WIZ hashing
> > -      * disable bit, which we don't touch here, but it's good
> > -      * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> > -      */
> > -     wa_add(wal,
> > -            GEN6_GT_MODE, 0,
> > -            _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
> > -            GEN6_WIZ_HASHING_16x4);
> > -
> > -     wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB);
> 
> Where did this go?

It was already in rcs_engine_wa
-Chris