[Intel-gfx] [PATCH] drm/i915/debugfs : PM_REQ and PM_RES register debugfs

[Jani Nikula]

[Stripped "--cc=" from Cc: addresses]

On Thu, 10 Dec 2020, Saichandana S <saichandana.s at intel.com> wrote:
> From: Saichandana <saichandana.s at intel.com>
>
> PM_REQ register provides the value of the last PM request from PCU to
> Display Engine.PM_RES register provides the value of the last PM response from
> Display Engine to PCU.
> This debugfs will be used by DC9 IGT test to know about "DC9 Ready"
> status.
> B.Spec : 49501, 49502
>
> Signed-off-by: Saichandana <saichandana.s at intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 24 +++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               |  5 ++++
>  2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cd7e5519ee7d..09e734e54032 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -559,6 +559,29 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  	return 0;
>  }
>  
> +static int i915_pm_req_res_info(struct seq_file *m, void *unused)
> +{
> +        struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +        struct intel_csr *csr = &dev_priv->csr;
> +
> +        if (!HAS_CSR(dev_priv))
> +                return -ENODEV;
> +
> +        if (!csr->dmc_payload)
> +                return 0;
> +
> +        seq_printf(m, "PM debug request 0 (0x45284) : 0x%x\n",
> +                        intel_de_read(dev_priv, PM_REQ_DBG_0));
> +        seq_printf(m, "PM debug request 1 (0x45288) : 0x%x\n",
> +                        intel_de_read(dev_priv, PM_REQ_DBG_1));
> +        seq_printf(m, "PM debug response 0 (0x4528C) : 0x%x\n",
> +                        intel_de_read(dev_priv, PM_RSP_DBG_0));
> +        seq_printf(m, "PM debug response 1 (0x45290) : 0x%x\n",
> +                        intel_de_read(dev_priv, PM_RSP_DBG_1));

IMO there is no point in providing a debugfs interface for reading and
dumping platform specific registers. Instead, you should provide a more
generic interface that parses the relevant information. Look at *all*
the other register reads in the i915_debugfs.c file. None of them output
the registers as-is.

BR,
Jani.

> +
> +        return 0;
> +}
> +
>  static void intel_seq_print_mode(struct seq_file *m, int tabs,
>  				 const struct drm_display_mode *mode)
>  {
> @@ -2100,6 +2123,7 @@ static const struct drm_info_list intel_display_debugfs_list[] = {
>  	{"i915_edp_psr_status", i915_edp_psr_status, 0},
>  	{"i915_power_domain_info", i915_power_domain_info, 0},
>  	{"i915_dmc_info", i915_dmc_info, 0},
> +	{"i915_pm_req_res_info", i915_pm_req_res_info, 0},
>  	{"i915_display_info", i915_display_info, 0},
>  	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
>  	{"i915_dp_mst_info", i915_dp_mst_info, 0},
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0023c023f472..b477a1f7b1bd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -371,6 +371,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define VLV_G3DCTL		_MMIO(0x9024)
>  #define VLV_GSCKGCTL		_MMIO(0x9028)
>  
> +#define PM_REQ_DBG_0		_MMIO(0x45284)
> +#define PM_REQ_DBG_1 		_MMIO(0x45288)
> +#define PM_RSP_DBG_0 		_MMIO(0x4528C)
> +#define PM_RSP_DBG_1 		_MMIO(0x45290)
> +
>  #define GEN6_MBCTL		_MMIO(0x0907c)
>  #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
>  #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)

-- 
Jani Nikula, Intel Open Source Graphics Center