[Intel-gfx] [PATCH 1/8] drm/i915/tgl: Extend Wa_1409825376 stepping

[Matt Roper]

On Fri, Feb 21, 2020 at 06:08:08PM -0800, José Roberto de Souza wrote:
> This workaround is only fixed in C0 stepping to extend it to B0 too.
> 
> BSpec: 52890
> Cc: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4305ccc4c683..57282b719ece 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1575,6 +1575,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  	(IS_ICELAKE(p) && IS_REVID(p, since, until))
>  
>  #define TGL_REVID_A0		0x0
> +#define TGL_REVID_B0		0x1

revid 1 is CPU + GT B0, but already has display C0 stepping
incorporated.  I forget...do the display workaround limits in the bspec
refer to display stepping or CPU/GT stepping?

For reference, bspec 44455.


Matt

>  
>  #define IS_TGL_REVID(p, since, until) \
>  	(IS_TIGERLAKE(p) && IS_REVID(p, since, until))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ffac0b862ca5..33149bccd117 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6852,7 +6852,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>  		   I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
>  
>  	/* Wa_1409825376:tgl (pre-prod)*/
> -	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> +	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>  		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
>  			   TGL_VRH_GATING_DIS);
>  }
> -- 
> 2.25.1
> 
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-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795