[Intel-gfx] [PATCH v2 14/14] drm/i915/tgl: Implement Wa_1407901919

[Chris Wilson]

Quoting José Roberto de Souza (2020-02-26 01:46:03)
> This will fix a memory coherence issue.
> 
> BSpec: 52890
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c |  6 ++++++
>  drivers/gpu/drm/i915/i915_reg.h             | 20 +++++++++++---------
>  2 files changed, 17 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 164b5e82e3e3..b3bb3dd90f02 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -606,6 +606,12 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>         wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
>                IS_TGL_GT_REVID(engine->i915, TGL_GT_REVID_A0,
>                                TGL_GT_REVID_A0) ? 0 : FF_MODE2_TDS_TIMER_MASK);
> +
> +       /* Wa_1407901919:tgl */
> +       wa_add(wal, ICL_HDC_MODE, HDC_COHERENT_ACCESS_L1_CACHE_DIS |
> +              HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W, 0,
> +              HDC_COHERENT_ACCESS_L1_CACHE_DIS |
> +              HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W);

Dropping by to say that is hard to read. Could you perhaps use
whitespace for visual grouping to an advantage?

	wa_write(wal, ICL_HDC_MODE,
		 HDC_COHERENT_ACCESS_L1_CACHE_DIS |
		 HDC_DIS_L1_INVAL_FOR_NON_L1_CACHEABLE_W);
-Chris