[Intel-gfx] [PATCH] drm/i915/tgl: Allow DC5/DC6 entry while PG2 is active

[Souza, Jose]

On Thu, 2020-02-20 at 15:18 -0800, Matt Roper wrote:
> On gen12, we no longer need to disable DC5/DC6 when when PG2 is in
> use
> (which translates to cases where we're using VDSC on pipe A).
> 
> Bspec: 49193

Reviewed-by: José Roberto de Souza <jose.souza at intel.com>

> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: José Roberto de Souza <jose.souza at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_power.c   | 16 +++++++++++---
> --
>  .../gpu/drm/i915/display/intel_display_power.h   |  1 +
>  2 files changed, 12 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 8ba68ec6dc24..1d21a850e933 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -926,10 +926,16 @@ void
> intel_display_power_set_target_dc_state(struct drm_i915_private
> *dev_priv,
>  
>  static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
>  {
> -	bool pg2_enabled =
> intel_display_power_well_is_enabled(dev_priv,
> -					SKL_DISP_PW_2);
> +	enum i915_power_well_id high_pg;
>  
> -	WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
> +	/* Power wells at this level and above must be disabled for DC5
> entry */
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		high_pg = TGL_DISP_PW_3;
> +	else
> +		high_pg = SKL_DISP_PW_2;
> +
> +	WARN_ONCE(intel_display_power_well_is_enabled(dev_priv,
> high_pg),
> +		  "Power wells above platform's DC5 limit still
> enabled.\n");
>  
>  	WARN_ONCE((intel_de_read(dev_priv, DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC5),
>  		  "DC5 already programmed to be enabled.\n");
> @@ -2712,7 +2718,7 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
>  	BIT_ULL(POWER_DOMAIN_INIT))
>  
>  #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
> -	TGL_PW_2_POWER_DOMAINS |			\
> +	TGL_PW_3_POWER_DOMAINS |			\
>  	BIT_ULL(POWER_DOMAIN_MODESET) |			\
>  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
>  	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> @@ -3908,7 +3914,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
>  		.name = "power well 3",
>  		.domains = TGL_PW_3_POWER_DOMAINS,
>  		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> +		.id = TGL_DISP_PW_3,
>  		{
>  			.hsw.regs = &hsw_power_well_regs,
>  			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 601e000ffd0d..da64a5edae7a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -100,6 +100,7 @@ enum i915_power_well_id {
>  	SKL_DISP_PW_MISC_IO,
>  	SKL_DISP_PW_1,
>  	SKL_DISP_PW_2,
> +	TGL_DISP_PW_3,
>  	SKL_DISP_DC_OFF,
>  };
>