[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL output/refclock tracking

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up DPLL output/refclock tracking
URL   : https://patchwork.freedesktop.org/series/73977/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
3ad933d04ce1 drm/i915: Fix bounds check in intel_get_shared_dpll_id()
649c52ce9987 drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c
0d005a5d024f drm/i915: Keep the global DPLL state in a DPLL specific struct
-:311: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#311: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:3835:
+	BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);

-:400: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#400: FILE: drivers/gpu/drm/i915/i915_drv.h:1057:
+		struct mutex lock;

total: 0 errors, 1 warnings, 1 checks, 339 lines checked
75d78cadd4ca drm/i915: Move the DPLL vfunc inits after the func defines
c6344edea0b3 drm/i915/hsw: Use the DPLL ID when calculating DPLL clock
60a8609aa55a drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c
-:607: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_810MHz>
#607: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1024:
+		if (pll == SPLL_FREQ_810MHz)

-:607: CHECK:BRACES: braces {} should be used on all arms of this statement
#607: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1024:
+		if (pll == SPLL_FREQ_810MHz)
[...]
+		else if (pll == SPLL_FREQ_1350MHz)
[...]
+		else if (pll == SPLL_FREQ_2700MHz)
[...]
+		else {
[...]

-:609: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#609: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1026:
+		else if (pll == SPLL_FREQ_1350MHz)

-:611: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_2700MHz>
#611: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1028:
+		else if (pll == SPLL_FREQ_2700MHz)

-:613: CHECK:BRACES: Unbalanced braces around else statement
#613: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1030:
+		else {

-:645: CHECK:LINE_SPACING: Please don't use multiple blank lines
#645: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1558:
+
+

-:787: CHECK:LINE_SPACING: Please don't use multiple blank lines
#787: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2593:
+
+

-:1001: CHECK:LINE_SPACING: Please don't use multiple blank lines
#1001: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:4339:
+
+

total: 0 errors, 0 warnings, 8 checks, 968 lines checked
fcb70a2a2063 drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it
b20cdae29985 drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL
08a1ec87a9d9 drm/i915/hsw: Split out the SPLL parameter calculation
-:29: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#29: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:969:
+	crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz |

total: 0 errors, 0 warnings, 1 checks, 51 lines checked
713fb8dc5a64 drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation
cd28115faa3a drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
-:519: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct drm_i915_private *' should also have an identifier name
#519: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:378:
+int intel_dpll_get_freq(struct drm_i915_private *,

-:519: WARNING:FUNCTION_ARGUMENTS: function definition argument 'const struct intel_shared_dpll *' should also have an identifier name
#519: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:378:
+int intel_dpll_get_freq(struct drm_i915_private *,

total: 0 errors, 2 warnings, 0 checks, 479 lines checked
fcda3e44c96b drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
a5e019011c6b drm/i915: Unify the DPLL ref clock frequency tracking