[Intel-gfx] [PATCH v2] drm/i915: Bump up CDCLK to eliminate underruns on TGL

[Matt Roper]

On Thu, Jan 09, 2020 at 06:58:16PM +0200, Stanislav Lisovskiy wrote:
> There seems to be some undocumented bandwidth
> bottleneck/dependency which scales with CDCLK,
> causing FIFO underruns when CDCLK is too low,
> even when it's correct from BSpec point of view.
> 
> Currently for TGL platforms we calculate
> min_cdclk initially based on pixel_rate divided
> by 2, accounting for also plane requirements,
> however in some cases the lowest possible CDCLK
> doesn't work and causing the underruns.

We probably want one more sentence here explaining the (somewhat blunt)
workaround we're actually applying with this patch.  E.g., "We've found
experimentally that raising cdclk to at least pixel_rate (rather than
pixel_rate/2) eliminates these underruns, so let's use this as a
temporary workaround until the hardware team can suggest a more precise
remedy."

> 
> Explicitly stating here that this seems to be currently
> rather a Hack, than final solution.
> 
> v2: Use clamp operation instead of min(Matt Roper)
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/402

I believe we're trying to start using "Closes:" rather than "Bugzilla:"
as the tag here now that the bug database isn't actually bugzilla
anymore.

Anyway, the patch does what it aims to do and eliminates the underruns
that are crippling us at the moment (at the expense of some higher power
usage), so with an updated commit message, this is

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 7d1ab1e5b7c3..23ef30175090 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2004,6 +2004,20 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	/* Account for additional needs from the planes */
>  	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>  
> +	/*
> +	 * HACK. Currently for TGL platforms we calculate
> +	 * min_cdclk initially based on pixel_rate divided
> +	 * by 2, accounting for also plane requirements,
> +	 * however in some cases the lowest possible CDCLK
> +	 * doesn't work and causing the underruns.
> +	 * Explicitly stating here that this seems to be currently
> +	 * rather a Hack, than final solution.
> +	 */
> +	if (IS_TIGERLAKE(dev_priv))
> +		min_cdclk = clamp(min_cdclk,
> +				  (int)crtc_state->pixel_rate,
> +				  (int)dev_priv->max_cdclk_freq);
> +
>  	if (min_cdclk > dev_priv->max_cdclk_freq) {
>  		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
>  			      min_cdclk, dev_priv->max_cdclk_freq);
> -- 
> 2.24.1.485.gad05a3d8e5
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795