[Intel-gfx] [V6 6/9] drm/i915/dsi: Configure TE interrupt for cmd mode

Jani Nikula jani.nikula at intel.com
Fri Jan 17 11:02:01 UTC 2020


On Thu, 09 Jan 2020, Vandita Kulkarni <vandita.kulkarni at intel.com> wrote:
> We need to configure TE interrupt in two places.
> Port interrupt and DSI interrupt mask registers.
>
> v2: Hide the private flags check inside configure_te (Jani)
>
> v3: Fix the position of masking de_port_masked for DSI_TE.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 55 +++++++++++++++++++++++++++++++--
>  1 file changed, 53 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index afc6aad9bf8c..3f6159708def 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -41,6 +41,7 @@
>  #include "display/intel_hotplug.h"
>  #include "display/intel_lpe_audio.h"
>  #include "display/intel_psr.h"
> +#include "display/intel_dsi.h"
>  
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_irq.h"
> @@ -2581,12 +2582,46 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
>  	return 0;
>  }
>  
> +static bool gen11_dsi_configure_te(struct drm_i915_private *dev_priv,
> +				   struct drm_display_mode *mode, bool enable)

Please pass just (struct intel_crtc *crtc, bool enable) to this
function, and the callers get simplified a lot.

> +{
> +	enum port port;
> +	u32 tmp;
> +
> +	if (!(mode->private_flags &
> +	    (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
> +		return false;
> +
> +	if (mode->private_flags & I915_MODE_FLAG_DSI_USE_TE1)
> +		port = PORT_B;
> +	else
> +		port = PORT_A;

This makes dual link use port B, is that right?

> +
> +	tmp =  I915_READ(DSI_INTR_MASK_REG(port));
> +	if (enable)
> +		tmp &= ~DSI_TE_EVENT;
> +	else
> +		tmp |= DSI_TE_EVENT;
> +
> +	I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
> +	return true;
> +}
> +
>  int bdw_enable_vblank(struct drm_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	enum pipe pipe = intel_crtc->pipe;
> +	struct drm_vblank_crtc *vblank;
> +	struct drm_display_mode *mode;
>  	unsigned long irqflags;
>  
> +	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
> +	mode = &vblank->hwmode;

With the parameter change to gen11_dsi_configure_te() all of the above
changes go away...

> +
> +	if (gen11_dsi_configure_te(dev_priv, mode, true))
> +		return 0;

...and this becomes simply

	if (gen11_dsi_configure_te(to_intel_crtc(crtc), true))

> +
>  	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>  	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> @@ -2652,9 +2687,18 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
>  void bdw_disable_vblank(struct drm_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	enum pipe pipe = intel_crtc->pipe;
> +	struct drm_vblank_crtc *vblank;
> +	struct drm_display_mode *mode;
>  	unsigned long irqflags;
>  
> +	vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
> +	mode = &vblank->hwmode;
> +
> +	if (gen11_dsi_configure_te(dev_priv, mode, false))
> +		return;
> +

Same here.

>  	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>  	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> @@ -3347,6 +3391,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
>  		de_port_masked |= CNL_AUX_CHANNEL_F;
>  
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		enum port port;
> +
> +		if (intel_bios_is_dsi_present(dev_priv, &port))
> +			de_port_masked |= DSI0_TE | DSI1_TE;
> +	}
> +
>  	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>  					   GEN8_PIPE_FIFO_UNDERRUN;

-- 
Jani Nikula, Intel Open Source Graphics Center


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