[Intel-gfx] [PATCH RESEND 4/6] drm/i915/gmbus: use intel de functions for forcewake register access
Ville Syrjälä
ville.syrjala at linux.intel.com
Thu Jan 23 14:13:41 UTC 2020
On Thu, Jan 23, 2020 at 04:00:02PM +0200, Jani Nikula wrote:
> Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and
> switch to using intel_de_read_fw() and intel_de_write_fw(),
> respectively. Also switch I915_READ() and I915_WRITE() over in this file
> while at it.
>
> No functional changes.
>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_gmbus.c | 74 ++++++++++------------
> 1 file changed, 35 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 3d4d19ac1d14..508308555dc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
<snip>
> @@ -404,15 +406,12 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
> len++;
> }
> size = len % 256 + 256;
> - I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
> + intel_de_write_fw(dev_priv, GMBUS0,
> + gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
> }
>
> - I915_WRITE_FW(GMBUS1,
> - gmbus1_index |
> - GMBUS_CYCLE_WAIT |
> - (size << GMBUS_BYTE_COUNT_SHIFT) |
> - (addr << GMBUS_SLAVE_ADDR_SHIFT) |
> - GMBUS_SLAVE_READ | GMBUS_SW_RDY);
> + intel_de_write_fw(dev_priv, GMBUS1,
> + gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
This one turned a bit ugly.
> while (len) {
> int ret;
> u32 val, loop = 0;
> @@ -421,7 +420,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
> if (ret)
> return ret;
>
> - val = I915_READ_FW(GMBUS3);
> + val = intel_de_read_fw(dev_priv, GMBUS3);
> do {
> if (extra_byte_added && len == 1)
> break;
> @@ -432,7 +431,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>
> if (burst_read && len == size - 4)
> /* Reset the override bit */
> - I915_WRITE_FW(GMBUS0, gmbus0_reg);
> + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg);
> }
>
> return 0;
> @@ -489,12 +488,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
> len -= 1;
> }
>
> - I915_WRITE_FW(GMBUS3, val);
> - I915_WRITE_FW(GMBUS1,
> - gmbus1_index | GMBUS_CYCLE_WAIT |
> - (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
> - (addr << GMBUS_SLAVE_ADDR_SHIFT) |
> - GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
> + intel_de_write_fw(dev_priv, GMBUS3, val);
> + intel_de_write_fw(dev_priv, GMBUS1,
> + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
ditto
> while (len) {
> int ret;
>
> @@ -503,7 +499,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
> val |= *buf++ << (8 * loop);
> } while (--len && ++loop < 4);
>
> - I915_WRITE_FW(GMBUS3, val);
> + intel_de_write_fw(dev_priv, GMBUS3, val);
>
> ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
> if (ret)
> @@ -568,7 +564,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
>
> /* GMBUS5 holds 16-bit index */
> if (gmbus5)
> - I915_WRITE_FW(GMBUS5, gmbus5);
> + intel_de_write_fw(dev_priv, GMBUS5, gmbus5);
>
> if (msgs[1].flags & I2C_M_RD)
> ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
> @@ -578,7 +574,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
>
> /* Clear GMBUS5 after each index transfer */
> if (gmbus5)
> - I915_WRITE_FW(GMBUS5, 0);
> + intel_de_write_fw(dev_priv, GMBUS5, 0);
>
> return ret;
> }
> @@ -601,7 +597,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> pch_gmbus_clock_gating(dev_priv, false);
>
> retry:
> - I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
> + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0);
>
> for (; i < num; i += inc) {
> inc = 1;
> @@ -629,7 +625,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> * a STOP on the very first cycle. To simplify the code we
> * unconditionally generate the STOP condition with an additional gmbus
> * cycle. */
> - I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
> + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
>
> /* Mark the GMBUS interface as disabled after waiting for idle.
> * We will re-enable it at the start of the next xfer,
> @@ -640,7 +636,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> adapter->name);
> ret = -ETIMEDOUT;
> }
> - I915_WRITE_FW(GMBUS0, 0);
> + intel_de_write_fw(dev_priv, GMBUS0, 0);
> ret = ret ?: i;
> goto out;
>
> @@ -669,9 +665,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> * of resetting the GMBUS controller and so clearing the
> * BUS_ERROR raised by the slave's NAK.
> */
> - I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
> - I915_WRITE_FW(GMBUS1, 0);
> - I915_WRITE_FW(GMBUS0, 0);
> + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT);
> + intel_de_write_fw(dev_priv, GMBUS1, 0);
> + intel_de_write_fw(dev_priv, GMBUS0, 0);
>
> DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
> adapter->name, msgs[i].addr,
> @@ -694,7 +690,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> timeout:
> DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
> bus->adapter.name, bus->reg0 & 0xff);
> - I915_WRITE_FW(GMBUS0, 0);
> + intel_de_write_fw(dev_priv, GMBUS0, 0);
>
> /*
> * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
> --
> 2.20.1
>
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> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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