[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Srivatsa, Anusha]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper at intel.com>
> Sent: Thursday, January 23, 2020 9:50 AM
> To: Srivatsa, Anusha <anusha.srivatsa at intel.com>
> Cc: intel-gfx at lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
> 
> On Wed, Jan 22, 2020 at 03:40:27PM -0800, Anusha Srivatsa wrote:
> > Disable Early Read and Src Swap by setting the bit 14 and 15 in the
> > chicken register.
> >
> > BSpec: 46045,52890
> > HSDES: 1606931601
> 
> Hmm.  The bspec WA description (which is very poorly written) only
> mentions setting bit 14, but comments in the HSD indicate that both 14 and
> 15 should be set.  Do we have offline confirmation/clarification about which
> we should trust?
> 
> If we do need to program both bits, it might still be a good idea to use two
> separate #define's for those rather than a single bitmask to make it more
> clear what we're doing and also to give us the option of just setting one or
> the other in case that winds up being necessary as a workaround for a
> different platform or future stepping.
> 
Going ahead with what the BSpec expects us to do - setting just bit 14. Sending v2 version shortly.

Anusha  

> Matt
> 
> >
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
> >  drivers/gpu/drm/i915/i915_reg.h             | 1 +
> >  2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 5a7db279f702..53b448b61a5f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> >  	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> >  	       IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> >  			    FF_MODE2_TDS_TIMER_MASK);
> > +
> > +	/* Wa_1606931601:tgl */
> > +	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> > +			  GEN11_EARLY_READ_SRC0_DISABLE_MASK);
> > +
> >  }
> >
> >  static void
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index b93c4c18f05c..69a1c2227b91
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9146,6 +9146,7 @@ enum {
> >  #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
> >  #define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
> >  #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
> > +#define   GEN11_EARLY_READ_SRC0_DISABLE_MASK
> 	REG_GENMASK(15, 14)
> >
> >  #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
> >  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
> > --
> > 2.23.0
> >
> > _______________________________________________
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> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795