[Intel-gfx] [PATCH v1] drm/i915: Clamp min_cdclk to max_cdclk_freq to unblock 8K

[Maarten Lankhorst]

Op 30-06-2020 om 13:26 schreef Stanislav Lisovskiy:
> We still need "Bump up CDCLK" workaround otherwise getting
> underruns - however currently it blocks 8K as CDCLK = Pixel rate,
> in 8K case would require CDCLK to be around 1 Ghz which is not
> possible.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 45f7f33d1144..01a5bc6b08c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2080,9 +2080,21 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	 * Explicitly stating here that this seems to be currently
>  	 * rather a Hack, than final solution.
>  	 */
> -	if (IS_TIGERLAKE(dev_priv))
> +	if (IS_TIGERLAKE(dev_priv)) {
>  		min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
>  
> +		/*
> +		 * Clamp to max_cdclk_freq in order not to break an 8K,
> +		 * but still leave W/A at place.
> +		 */
> +		min_cdclk = min(min_cdclk, (int)dev_priv->max_cdclk_freq);
> +
> +		/*
> +		 * max_cdclk_freq check obviously not needed - just return.
> +		 */
> +		return min_cdclk;
> +	}
> +
>  	if (min_cdclk > dev_priv->max_cdclk_freq) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "required cdclk (%d kHz) exceeds max (%d kHz)\n",

Wouldn't you just have to halve pixel_rate if bigjoiner flag is set?