[Intel-gfx] [PATCH 4/4] drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865

[Souza, Jose]

On Thu, 2020-07-02 at 18:37 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Normally i85x/i865 3D activity will block FBC until a 2D blit
> occurs. I suppose this was meant to avoid recompression while
> 3D activity is still going on but the frame hasn't yet been
> presented. Unfortunately that also means that a page flipped
> 3D workload will permanently block FBC even if it only renders
> a single frame and then does nothing.
> 
> Since we are using software render tracking anyway we might as
> well flip the chicken bit so that 3D does not block FBC. This
> will avoid the permament FBC blockage in the aforemention use
> case, but thanks to the software tracking the compressor will
> not disturb 3D rendering activity.

Register does what is described.

Reviewed-by: José Roberto de Souza <jose.souza at intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9d6536afc94b..03590d2d75f7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2827,6 +2827,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
>  #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
>  #define SCPD0		_MMIO(0x209c) /* 915+ only */
> +#define  SCPD_FBC_IGNORE_3D			(1 << 6)
>  #define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
>  #define GEN2_IER	_MMIO(0x20a0)
>  #define GEN2_IIR	_MMIO(0x20a4)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 565a2b9da3b3..2d980b83a1f1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7471,6 +7471,16 @@ static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>  	I915_WRITE(MEM_MODE,
>  		   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
> +
> +	/*
> +	 * Have FBC ignore 3D activity since we use software
> +	 * render tracking, and otherwise a pure 3D workload
> +	 * (even if it just renders a single frame and then does
> +	 * abosultely nothing) would not allow FBC to recompress
> +	 * until a 2D blit occurs.
> +	 */
> +	I915_WRITE(SCPD0,
> +		   _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
>  }
>  
>  static void i830_init_clock_gating(struct drm_i915_private *dev_priv)