[Intel-gfx] [PATCH 10/66] drm/i915: Soften the tasklet flush frequency before waits

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> We include a tasklet flush before waiting on a request as a precaution
> against the HW being lax in event signaling. We now have a precautionary
> flush in the engine's heartbeat and so do not need to be quite so
> zealous on every request wait. If we focus on the request, the only
> tasklet flush that matters is if there is a delay in submitting this
> request to HW, so if the request is not ready to be executed no
> advantage in reducing this wait can be gained by running the tasklet.
> And there is little point in doing busy work for no result.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_request.c | 20 ++++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index 29b5e71307e3..f58beff5e859 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -1760,14 +1760,30 @@ long i915_request_wait(struct i915_request *rq,
>  	if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
>  		goto out;
>  
> +	/*
> +	 * Flush the submission tasklet, but only if it may help this request.
> +	 *
> +	 * We sometimes experience some latency between the HW interrupts and
> +	 * tasklet execution (mostly due to ksoftirqd latency, but it can also
> +	 * be due to lazy CS events), so lets run the tasklet manually if there
> +	 * is a chance it may submit this request. If the request is not ready
> +	 * to run, as it is waiting for other fences to be signaled, flushing
> +	 * the tasklet is busy work without any advantage for this client.
> +	 *
> +	 * If the HW is being lazy, this is the last chance before we go to
> +	 * sleep to catch any pending events. We will check periodically in
> +	 * the heartbeat to flush the submission tasklets as a last resort
> +	 * for unhappy HW.
> +	 */
> +	if (i915_request_is_ready(rq))
> +		intel_engine_flush_submission(rq->engine);
> +
>  	for (;;) {
>  		set_current_state(state);
>  
>  		if (dma_fence_is_signaled(&rq->fence))
>  			break;
>  
> -		intel_engine_flush_submission(rq->engine);
> -
>  		if (signal_pending_state(state, current)) {
>  			timeout = -ERESTARTSYS;
>  			break;
> -- 
> 2.20.1