[Intel-gfx] [PATCH 2/2] drm/i915/gt: Wait for aux invalidation on Tigerlake

[Chris Wilson]

Quoting Chris Wilson (2020-07-16 21:32:01)
> Add a SRM read back of the aux invalidation register after poking
> hsdes: 1809175790, as failing to do so leads to writes going astray.
> 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2169
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 31 ++++++++++++++++++++++-------
>  1 file changed, 24 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index e0280a672f1d..c9e46792b976 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -4757,14 +4757,21 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode)
>         intel_engine_mask_t aux_inv = 0;
>         u32 cmd, *cs;
>  
> +       cmd = 4;
> +       if (mode & EMIT_INVALIDATE)
> +               cmd += 2;
>         if (mode & EMIT_INVALIDATE)
>                 aux_inv = request->engine->mask & ~BIT(BCS0);
> +       if (aux_inv)
> +               cmd += 2 * hweight8(aux_inv) + 6;
>  
> -       cs = intel_ring_begin(request,
> -                             4 + (aux_inv ? 2 * hweight8(aux_inv) + 2 : 0));
> +       cs = intel_ring_begin(request, cmd);
>         if (IS_ERR(cs))
>                 return PTR_ERR(cs);
>  
> +       if (mode & EMIT_INVALIDATE)
> +               *cs++ = preparser_disable(true);
> +
>         cmd = MI_FLUSH_DW + 1;
>  
>         /* We always require a command barrier so that subsequent
> @@ -4780,11 +4787,6 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode)
>                         cmd |= MI_INVALIDATE_BSD;
>         }
>  
> -       *cs++ = cmd;
> -       *cs++ = LRC_PPHWSP_SCRATCH_ADDR;
> -       *cs++ = 0; /* upper addr */
> -       *cs++ = 0; /* value */
> -
>         if (aux_inv) { /* hsdes: 1809175790 */
>                 struct intel_engine_cs *engine;
>                 unsigned int tmp;
> @@ -4796,7 +4798,22 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode)
>                         *cs++ = AUX_INV;
>                 }
>                 *cs++ = MI_NOOP;
> +
> +               *cs++ = MI_STORE_REGISTER_MEM | MI_USE_GGTT;

Sigh. So I fixed this to MI_SRM_GEN8 and tgl failed the test again.

> +               *cs++ = i915_mmio_reg_offset(aux_inv_reg(request->engine));
> +               *cs++ = i915_ggtt_offset(engine->status_page.vma) +
> +                       I915_GEM_HWS_SCRATCH * sizeof(u32);
> +               *cs++ = 0;

-Chris