[Intel-gfx] [PATCH v8 3/5] drm/i915/rkl: Add DPLL4 support
Lucas De Marchi
lucas.demarchi at intel.com
Fri Jul 17 05:39:05 UTC 2020
On Thu, Jul 16, 2020 at 03:05:49PM -0700, Matt Roper wrote:
>Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
>enable a third display. Unlike EHL's variant of DPLL4, the RKL variant
>behaves the same as DPLL0/1. And despite its name, the DPLL4 registers
>are offset as if it were DPLL2.
>
>v2:
> - Add new .update_ref_clks() hook.
>
>v3:
> - Renumber TBT PLL to '3' and switch _MMIO_PLL3 to _MMIO_PLL (Lucas)
>
>v4:
> - Don't drop _MMIO_PLL3; although it's now unused, we're going to need
> it very soon again for upcoming DG1 patches. (Lucas)
>
>v5:
> - Don't re-number TBT PLL and beyond, just use new RKL_DPLL_CFGCR
> macros to lookup the proper registers instead. Although renumbering
> the PLLs might be something we want to consider down the road, it
> opens a big can of worms right now since a bunch of places in the
> code have an assumption that the PLL table has idx==id and no holes.
> Renumbering creates a hole for TGL, so we'd either need to allow
> holes in the table or break the idx==id invariant, both of which are
> somewhat invasive changes to the design.
>
>Bspec: 49202
>Bspec: 49443
>Bspec: 50288
>Bspec: 50289
>Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>Cc: José Roberto de Souza <jose.souza at intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 41 ++++++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++-
> 2 files changed, 40 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>index aeb6ee395cce..134c2ecf4c80 100644
>--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>@@ -3504,13 +3504,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>
> icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>
>- if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
>+ if (IS_ROCKETLAKE(dev_priv)) {
> dpll_mask =
> BIT(DPLL_ID_EHL_DPLL4) |
> BIT(DPLL_ID_ICL_DPLL1) |
> BIT(DPLL_ID_ICL_DPLL0);
>- else
>+ } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) {
>+ dpll_mask =
>+ BIT(DPLL_ID_EHL_DPLL4) |
>+ BIT(DPLL_ID_ICL_DPLL1) |
>+ BIT(DPLL_ID_ICL_DPLL0);
>+ } else {
> dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0);
>+ }
>
> port_dpll->pll = intel_find_shared_dpll(state, crtc,
> &port_dpll->hw_state,
>@@ -3791,7 +3797,12 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> if (!(val & PLL_ENABLE))
> goto out;
>
>- if (INTEL_GEN(dev_priv) >= 12) {
>+ if (IS_ROCKETLAKE(dev_priv)) {
>+ hw_state->cfgcr0 = intel_de_read(dev_priv,
>+ RKL_DPLL_CFGCR0(id));
>+ hw_state->cfgcr1 = intel_de_read(dev_priv,
>+ RKL_DPLL_CFGCR1(id));
>+ } else if (INTEL_GEN(dev_priv) >= 12) {
> hw_state->cfgcr0 = intel_de_read(dev_priv,
> TGL_DPLL_CFGCR0(id));
> hw_state->cfgcr1 = intel_de_read(dev_priv,
>@@ -3844,7 +3855,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
> const enum intel_dpll_id id = pll->info->id;
> i915_reg_t cfgcr0_reg, cfgcr1_reg;
>
>- if (INTEL_GEN(dev_priv) >= 12) {
>+ if (IS_ROCKETLAKE(dev_priv)) {
>+ cfgcr0_reg = RKL_DPLL_CFGCR0(id);
>+ cfgcr1_reg = RKL_DPLL_CFGCR1(id);
>+ } else if (INTEL_GEN(dev_priv) >= 12) {
> cfgcr0_reg = TGL_DPLL_CFGCR0(id);
> cfgcr1_reg = TGL_DPLL_CFGCR1(id);
> } else {
>@@ -4276,6 +4290,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
> .dump_hw_state = icl_dump_hw_state,
> };
>
>+static const struct dpll_info rkl_plls[] = {
>+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
>+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
>+ { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
>+ { },
>+};
>+
>+static const struct intel_dpll_mgr rkl_pll_mgr = {
>+ .dpll_info = rkl_plls,
>+ .get_dplls = icl_get_dplls,
>+ .put_dplls = icl_put_dplls,
>+ .update_ref_clks = icl_update_dpll_ref_clks,
>+ .dump_hw_state = icl_dump_hw_state,
>+};
>+
> /**
> * intel_shared_dpll_init - Initialize shared DPLLs
> * @dev: drm device
>@@ -4289,7 +4318,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
> const struct dpll_info *dpll_info;
> int i;
>
>- if (INTEL_GEN(dev_priv) >= 12)
>+ if (IS_ROCKETLAKE(dev_priv))
>+ dpll_mgr = &rkl_pll_mgr;
>+ else if (INTEL_GEN(dev_priv) >= 12)
> dpll_mgr = &tgl_pll_mgr;
> else if (IS_ELKHARTLAKE(dev_priv))
> dpll_mgr = &ehl_pll_mgr;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 00414c457941..bfdb6d23b5d8 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10511,19 +10511,21 @@ enum skl_power_gate {
>
> #define _TGL_DPLL0_CFGCR0 0x164284
> #define _TGL_DPLL1_CFGCR0 0x16428C
>-/* TODO: add DPLL4 */
> #define _TGL_TBTPLL_CFGCR0 0x16429C
> #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
> _TGL_DPLL1_CFGCR0, \
> _TGL_TBTPLL_CFGCR0)
>+#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
>+ _TGL_DPLL1_CFGCR0)
>
> #define _TGL_DPLL0_CFGCR1 0x164288
> #define _TGL_DPLL1_CFGCR1 0x164290
>-/* TODO: add DPLL4 */
> #define _TGL_TBTPLL_CFGCR1 0x1642A0
> #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
> _TGL_DPLL1_CFGCR1, \
> _TGL_TBTPLL_CFGCR1)
>+#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
>+ _TGL_DPLL1_CFGCR1)
>
> #define _DKL_PHY1_BASE 0x168000
> #define _DKL_PHY2_BASE 0x169000
>--
>2.24.1
>
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