[Intel-gfx] [PATCH 1/3] drm/i915/perf: Whitelist OA report trigger registers

[Lionel Landwerlin]

On 17/07/2020 04:57, Umesh Nerlige Ramappa wrote:
> From: Piotr Maciejewski <piotr.maciejewski at intel.com>
>
> OA reports can be triggered into the OA buffer by writing into the
> OAREPORTTRIG registers. Whitelist the registers to allow user to trigger
> reports.
>
> Signed-off-by: Piotr Maciejewski <piotr.maciejewski at intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +++++++++++++++++++++
>   1 file changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5726cd0a37e0..582a2c8cd219 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1365,6 +1365,20 @@ whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
>   	whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
>   }
>   
> +static void gen9_whitelist_build_performance_counters(struct i915_wa_list *w)
> +{
> +	/* OA buffer trigger report 2/6 used by performance query */
> +	whitelist_reg(w, OAREPORTTRIG2);
> +	whitelist_reg(w, OAREPORTTRIG6);
> +}
> +
> +static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
> +{
> +	/* OA buffer trigger report 2/6 used by performance query */
> +	whitelist_reg(w, GEN12_OAG_OAREPORTTRIG2);
> +	whitelist_reg(w, GEN12_OAG_OAREPORTTRIG6);
> +}
> +
>   static void gen9_whitelist_build(struct i915_wa_list *w)
>   {
>   	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
> @@ -1378,6 +1392,9 @@ static void gen9_whitelist_build(struct i915_wa_list *w)
>   
>   	/* WaSendPushConstantsFromMMIO:skl,bxt */
>   	whitelist_reg(w, COMMON_SLICE_CHICKEN2);
> +
> +	/* Performance counters support */
> +	gen9_whitelist_build_performance_counters(w);
>   }
>   
>   static void skl_whitelist_build(struct intel_engine_cs *engine)
> @@ -1471,6 +1488,9 @@ static void cnl_whitelist_build(struct intel_engine_cs *engine)
>   
>   	/* WaEnablePreemptionGranularityControlByUMD:cnl */
>   	whitelist_reg(w, GEN8_CS_CHICKEN1);
> +
> +	/* Performance counters support */
> +	gen9_whitelist_build_performance_counters(w);
>   }
>   
>   static void icl_whitelist_build(struct intel_engine_cs *engine)
> @@ -1500,6 +1520,9 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>   		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
>   				  RING_FORCE_TO_NONPRIV_ACCESS_RD |
>   				  RING_FORCE_TO_NONPRIV_RANGE_4);
> +
> +		/* Performance counters support */
> +		gen9_whitelist_build_performance_counters(w);
>   		break;
>   
>   	case VIDEO_DECODE_CLASS:
> @@ -1550,6 +1573,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
>   
>   		/* Wa_1806527549:tgl */
>   		whitelist_reg(w, HIZ_CHICKEN);
> +
> +		/* Performance counters support */
> +		gen12_whitelist_build_performance_counters(w);
>   		break;
>   	default:
>   		whitelist_reg_ext(w,

Since this is a i915-perf feature, I think we should bump the i915-perf 
revision number.

This will allow the IGT test to properly check the availability of this 
feature and skip otherwise.


Otherwise looks sound to me.


-Lionel