[Intel-gfx] [PATCH] drm/i915/tgl: Make sure TC-cold is blocked before enabling TC AUX power wells

Souza, Jose jose.souza at intel.com
Mon Jul 20 23:34:04 UTC 2020


On Tue, 2020-07-21 at 02:29 +0300, Imre Deak wrote:
> The dependency between power wells is determined by the ordering of the
> power well list: when enabling the power wells for a domain, this
> happens walking the power well list forward, while disabling them
> happens in the reverse direction. Accordingly a power well on the list
> must follow any other power well it depends on.
> 
> Since the TC AUX power wells depend on TC-cold being blocked, move the
> TC-cold off power well before all AUX power wells.
> 

Reviewed-by: José Roberto de Souza <jose.souza at intel.com>

> Fixes: 3c02934b24e ("Implement TC cold sequences")
> Cc: José Roberto de Souza <
> jose.souza at intel.com
> >
> Signed-off-by: Imre Deak <
> imre.deak at intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 0c713e83274d..c2aaf6911e7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4146,6 +4146,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>  			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
>  		},
>  	},
> +	{
> +		.name = "TC cold off",
> +		.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
> +		.ops = &tgl_tc_cold_off_ops,
> +		.id = DISP_PW_ID_NONE,
> +	},
>  	{
>  		.name = "AUX A",
>  		.domains = TGL_AUX_A_IO_POWER_DOMAINS,
> @@ -4332,12 +4338,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>  			.hsw.irq_pipe_mask = BIT(PIPE_D),
>  		},
>  	},
> -	{
> -		.name = "TC cold off",
> -		.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
> -		.ops = &tgl_tc_cold_off_ops,
> -		.id = DISP_PW_ID_NONE,
> -	},
>  };
>  
>  static const struct i915_power_well_desc rkl_power_wells[] = {
> 


More information about the Intel-gfx mailing list