[Intel-gfx] [PATCH 2/2] drm/i915/gt: Stall around xcs invalidations on tgl

[Chris Wilson]

Quoting Chris Wilson (2020-07-23 18:41:44)
> Whether this is an arbitrary stall or a vital ingredient, neverthess the
> impact is noticeable. If we do not have the stall around the xcs
> invalidation before a request, writes within that request sometimes go
> astray.
> 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2169
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 353b1717fe84..7767459549a5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -4761,10 +4761,12 @@ static int gen12_emit_flush_render(struct i915_request *request,
>  
>  static int gen12_emit_flush(struct i915_request *request, u32 mode)
>  {
> +#define WA_CNT 12 /* Magic delay or size of some internal pipelined buffer? */

12 is not enough. I repeat, 12 is not enough.
-Chris