[Intel-gfx] [PATCH] drm/i915: Correct location of Wa_1408615072

[Daniele Ceraolo Spurio]

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>

Daniele

On 7/10/2020 2:32 PM, John.C.Harrison at Intel.com wrote:
> From: John Harrison <John.C.Harrison at Intel.com>
>
> The above workaround was added as an engine workaround not a GT
> workaround. Moved it to the correct location.
>
> Signed-off-by: John Harrison <John.C.Harrison at Intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++----
>   1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5726cd0a37e0..a6548a77439c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1191,6 +1191,12 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>   		wa_write_or(wal,
>   			    SLICE_UNIT_LEVEL_CLKGATE,
>   			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> +
> +	/* Wa_1408615072:tgl[a0] */
> +	/* Empirical testing shows this register is unaffected by engine reset. */
> +	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> +		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> +			    VSUNIT_CLKGATE_DIS_TGL);
>   }
>   
>   static void
> @@ -1648,10 +1654,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>   		wa_write_or(wal,
>   			    GEN7_SARCHKMD,
>   			    GEN7_DISABLE_SAMPLER_PREFETCH);
> -
> -		/* Wa_1408615072:tgl */
> -		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> -			    VSUNIT_CLKGATE_DIS_TGL);
>   	}
>   
>   	if (IS_TIGERLAKE(i915)) {