[Intel-gfx] [PATCH 3/4] drm/i915/perf: Whitelist OA counter and buffer registers

[Umesh Nerlige Ramappa]

On Fri, Jul 24, 2020 at 09:55:35AM +0100, Chris Wilson wrote:
>Quoting Umesh Nerlige Ramappa (2020-07-24 01:19:00)
>> From: Piotr Maciejewski <piotr.maciejewski at intel.com>
>>
>> It is useful to have markers in the OA reports to identify triggered
>> reports. Whitelist some OA counters that can be used as markers.
>>
>> A triggered report can be found faster if we can sample the HW tail and
>> head registers when the report was triggered. Whitelist OA buffer
>> specific registers.
>>
>> v2:
>> - Bump up the perf revision (Lionel)
>> - Use indexing for counters (Lionel)
>> - Fix selftest for oa ticking register (Umesh)
>>
>> v3: Pardon whitelisted registers for selftest (Umesh)
>>
>> v4:
>> - Document whitelisted registers (Lionel)
>> - Fix live isolated whitelist for OA regs (Umesh)
>>
>> Signed-off-by: Piotr Maciejewski <piotr.maciejewski at intel.com>
>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
>> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 34 +++++++++++++++++++
>>  .../gpu/drm/i915/gt/selftest_workarounds.c    | 30 +++++++++++++++-
>>  drivers/gpu/drm/i915/i915_perf.c              |  8 ++++-
>>  drivers/gpu/drm/i915/i915_reg.h               | 10 ++++++
>>  4 files changed, 80 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index a72ebfd115e5..c950d07beec3 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -1392,6 +1392,23 @@ static void gen9_whitelist_build_performance_counters(struct i915_wa_list *w)
>>         /* OA buffer trigger report 2/6 used by performance query */
>>         whitelist_reg(w, OAREPORTTRIG2);
>>         whitelist_reg(w, OAREPORTTRIG6);
>> +
>> +       /* Performance counters A18-20 used by tbs marker query */
>> +       whitelist_reg_ext(w, OA_PERF_COUNTER_A(18),
>> +                         RING_FORCE_TO_NONPRIV_ACCESS_RW |
>> +                         RING_FORCE_TO_NONPRIV_RANGE_4);
>> +
>> +       whitelist_reg(w, OA_PERF_COUNTER_A(20));
>> +       whitelist_reg(w, OA_PERF_COUNTER_A_UPPER(20));
>> +
>> +       /* Read access to gpu ticks */
>> +       whitelist_reg_ext(w, GEN8_GPU_TICKS,
>> +                         RING_FORCE_TO_NONPRIV_ACCESS_RD);
>> +
>> +       /* Read access to: oa status, head, tail, buffer settings */
>> +       whitelist_reg_ext(w, GEN8_OASTATUS,
>> +                         RING_FORCE_TO_NONPRIV_ACCESS_RD |
>> +                         RING_FORCE_TO_NONPRIV_RANGE_4);
>
>Great. This completely fills RING_MAX_NONPRIV_SLOTS, with over half the
>slots going to OA. That does not seem sustainable.
>
>I did not think the extended whitelist settings were available before
>cml.

Looks like we can remove A20, A20_upper and gpu ticks to free up 3 
slots. Will post that in the new series. Hoping that will do for now.

Thanks,
Umesh

>-Chris