[Intel-gfx] [PATCH 1/4] drm/i915/perf: Ensure observation logic is not clock gated

[Chris Wilson]

Quoting Umesh Nerlige Ramappa (2020-07-31 07:07:20)
> From: Piotr Maciejewski <piotr.maciejewski at intel.com>
> 
> A clock gating switch can control if the performance monitoring and
> observation logic is enaled or not. Ensure that we enable the clocks.
> 
> v2: Separate code from other patches (Lionel)
> v3: Reset PMON enable when disabling perf to save power (Lionel)
> 
> Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
> Signed-off-by: Piotr Maciejewski <piotr.maciejewski at intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_perf.c | 13 +++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h  |  2 ++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index c6f6370283cf..fe408c327d3c 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2493,6 +2493,14 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
>                             (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
>                             : 0);
>  
> +       /*
> +        * Initialize Super Queue Internal Cnt Register
> +        * Set PMON Enable in order to collect valid metrics.
> +        */
> +       intel_uncore_write(uncore, GEN12_SQCNT1,
> +                          intel_uncore_read(uncore, GEN12_SQCNT1) |
> +                          GEN12_SQCNT1_PMON_ENABLE);

intel_uncore_rmw(uncore, GEN12_SQCNT, 0 GEN12_SQCNT1_PMON_ENABLE);

> +
>         /*
>          * Update all contexts prior writing the mux configurations as we need
>          * to make sure all slices/subslices are ON before writing to NOA
> @@ -2552,6 +2560,11 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream)
>  
>         /* Make sure we disable noa to save power. */
>         intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
> +
> +       /* Reset PMON Enable to save power. */
> +       intel_uncore_write(uncore, GEN12_SQCNT1,
> +                          intel_uncore_read(uncore, GEN12_SQCNT1) &
> +                          ~GEN12_SQCNT1_PMON_ENABLE);

intel_uncore_rmw(uncore, GEN12_SQCNT, GEN12_SQCNT1_PMON_ENABLE, 0);

Tempting to suggest we add intel_uncore_set_bit/clr_bit helpers around
the rmw helper.

>  }
>  
>  static void gen7_oa_enable(struct i915_perf_stream *stream)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5eae593ee784..377339399458 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -696,6 +696,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define OABUFFER_SIZE_16M   (7 << 3)
>  
>  #define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
> +#define GEN12_SQCNT1 _MMIO(0x8718)
> +#define  GEN12_SQCNT1_PMON_ENABLE (1 << 30)

REG_BIT(30)
-Chris