[Intel-gfx] [PATCH] drm/i915/tgl: Implement WA_16011163337

[Chris Wilson]

Quoting clinton.a.taylor at intel.com (2020-06-02 20:25:01)
> From: Clint Taylor <clinton.a.taylor at intel.com>
> 
> Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2
> not being able to be read.
> 
> Cc: Caz Yokoyama <caz.yokoyama at intel.com>
> Cc: Matt Atwood <matthew.s.atwood at intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++----
>  drivers/gpu/drm/i915/i915_reg.h             | 2 ++
>  2 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index fa1e15657663..7bc6474cce0e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -594,11 +594,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>          * Wa_1604555607:gen12 and Wa_1608008084:gen12
>          * FF_MODE2 register will return the wrong value when read. The default
>          * value for this register is zero for all fields and there are no bit
> -        * masks. So instead of doing a RMW we should just write the TDS timer
> -        * value for Wa_1604555607.
> +        * masks. So instead of doing a RMW we should just write the GS Timer
> +        * and TDS timer values for Wa_1604555607 and Wa_16011163337.
>          */
> -       wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
> -              FF_MODE2_TDS_TIMER_128, 0);
> +       wa_add(wal, FF_MODE2, FF_MODE2_GS_TIMER_MASK & FF_MODE2_TDS_TIMER_MASK,

GS_TIMER_MASK & TDS_TIMER_MASK is 0

I think you meant |
-Chris