[Intel-gfx] [PATCH] drm/i915/display: Avoid PSR and FBC features concurently.

[Le, Jason V]

I had a meeting with an Intel Display Architect.  The expected behavior for the driver is PSR2-SU enabling should disable FBC.  I will update the patch to limit fbc disabling for PSR2-SU only, not PSR1.  Please look at the HSD below for expected driver implementation.  
https://hsdes.intel.com/appstore/article/#/14010265390  
Thanks,
Jason

-----Original Message-----
From: Souza, Jose <jose.souza at intel.com> 
Sent: Monday, June 08, 2020 9:52 AM
To: Le, Jason V <jason.v.le at intel.com>; intel-gfx at lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Avoid PSR and FBC features concurently.

On Sun, 2020-06-07 at 23:56 -0700, Jason Le wrote:
> Issue: Enble both PSR and FBC caused some fickers on some eDP panels 
> (eg. Panel GIS 13.5" QHD Glare NE135FBM-N41/NC135GFL02).  Disbling 
> either PSR or FBC will solve this flicker issue.
> 
> Both PSR and FBC features save power when render is not busy. When PSR 
> is active, saving power achieved  by source turning off source 
> transmitter and main link, putting memory on self-refresh mode. 
> Therefore with PSR enabled, FBC role is minimized since PSR power 
> saving already covers most what FBC does.  Disabling FBC in case to 
> avoid conflict between PSR and FBC which causes display anomaly in some scenarios.

The combination of both saves even more power so no to this, we should fix the issue not disable features because of a single panel having issues.

A PSR2 fix was merged yesterday "drm/i915/psr: Program default IO buffer Wake and Fast Wake" try with that, if just that don't fix try set psr_safest_params=1.
If this do not helps, please file a bug, add debug information and then we proceed from that.

> 
> Tests:
> Booted system with PSR enabled, verified FBC disabled.
> Disabled PSR with disabled (i915.enable_psr=0), verified FBC enabled.
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++++++  
> drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 1c26673acb2d..52bc7483adb5 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1419,6 +1419,12 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
>  	drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n",
>  		    i915_modparams.enable_fbc);
>  
> +	if (i915_modparams.enable_psr) {
> +               i915_modparams.enable_fbc = 0;
> +                DRM_DEBUG_KMS("PSR enabled. FBC no longer needed.  Disable FBC. \n");
> +	}
> +
> +
>  	if (!HAS_FBC(dev_priv)) {
>  		fbc->no_fbc_reason = "unsupported by this chipset";
>  		return;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b7a2c102648a..25accfdd5ad3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1439,8 +1439,10 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
>  	if (!HAS_PSR(dev_priv))
>  		return;
>  
> -	if (!dev_priv->psr.sink_support)
> +	if (!dev_priv->psr.sink_support) {
> +		i915_modparams.enable_psr = 0;
>  		return;
> +	}
>  
>  	if (IS_HASWELL(dev_priv))
>  		/*