[Intel-gfx] [PATCH] drm/i915/display: Fix the encoder type check

[Shankar, Uma]

> -----Original Message-----
> From: Kulkarni, Vandita <vandita.kulkarni at intel.com>
> Sent: Friday, June 12, 2020 1:53 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar at intel.com>; Kulkarni, Vandita
> <vandita.kulkarni at intel.com>
> Subject: [PATCH] drm/i915/display: Fix the encoder type check
> 
> For all ddi, encoder->type holds output type as ddi, assigning it to individual o/p
> types is no more valid.
> 
> Fixes: 362bfb995b78 ("drm/i915/tgl: Add DKL PHY vswing table for HDMI")
> 
> v2: Rebase, no functional change.

Pushed the change to dinq. Thanks for the patch.

Regards,
Uma Shankar

> Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com>
> Reviewed-by: Uma Shankar <uma.shankar at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d1acc39cdc11..ca7bb2294d2b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2615,7 +2615,7 @@ static void icl_ddi_vswing_sequence(struct
> intel_encoder *encoder,
> 
>  static void
>  tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
> -				u32 level)
> +				u32 level, enum intel_output_type type)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); @@ -
> 2623,7 +2623,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder
> *encoder, int link_clock,
>  	u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
>  	int rate = 0;
> 
> -	if (encoder->type != INTEL_OUTPUT_HDMI) {
> +	if (type == INTEL_OUTPUT_HDMI) {
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> 
>  		rate = intel_dp->link_rate;
> @@ -2676,7 +2676,7 @@ static void tgl_ddi_vswing_sequence(struct
> intel_encoder *encoder,
>  	if (intel_phy_is_combo(dev_priv, phy))
>  		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
>  	else
> -		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
> +		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level,
> type);
>  }
> 
>  static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
> --
> 2.21.0.5.gaeb582a