[Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling
Imre Deak
imre.deak at intel.com
Mon Jun 22 18:35:09 UTC 2020
On Wed, Jun 17, 2020 at 05:42:28PM -0700, Lucas De Marchi wrote:
> DG1 has one more combo phy port, no TC and all irq handling goes through
> SDE, like for MCC.
>
> Cc: Anshuman Gupta <anshuman.gupta at intel.com>
> Cc: José Roberto de Souza <jose.souza at intel.com>
> Cc: Imre Deak <imre.deak at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 8 +++++
> 2 files changed, 59 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 48e1686df3416..3707f9231171f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
> [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
> };
>
> +static const u32 hpd_dg1_sde[HPD_NUM_PINS] = {
> + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A),
> + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B),
> + [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C),
> + [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D),
The above 2 entries look incorrect. encoder->hpd_pin will be assigned
based on the encoder/port's PHY (see intel_hpd_pin_default()). On DG1
port D is connected to PHY C and port E is connected to PHY D. So the
above two pin definitions should be:
[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PHY_C),
[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_D),
> +};
> +
> static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> {
> struct i915_hotplug *hpd = &dev_priv->hotplug;
> @@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> else
> hpd->hpd = hpd_ilk;
>
> - if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
> + if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
> + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
> return;
>
> - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> + if (HAS_PCH_DG1(dev_priv))
> + hpd->pch_hpd = hpd_dg1_sde;
> + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
> hpd->pch_hpd = hpd_tgp;
> else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
> hpd->pch_hpd = hpd_icp;
> @@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> }
> }
>
> +static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> +{
> + switch (pin) {
> + case HPD_PORT_A:
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
> + case HPD_PORT_B:
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
> + case HPD_PORT_D:
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
> + case HPD_PORT_E:
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
> + default:
> + return false;
> + }
> +}
> +
> static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
> {
> switch (pin) {
> @@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> u32 ddi_hotplug_trigger, tc_hotplug_trigger;
> u32 pin_mask = 0, long_mask = 0;
> bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
> + bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
>
> - if (HAS_PCH_TGP(dev_priv)) {
> + if (HAS_PCH_DG1(dev_priv)) {
> + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
> + ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect;
> + tc_hotplug_trigger = 0;
> + } else if (HAS_PCH_TGP(dev_priv)) {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
> tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
> } else if (HAS_PCH_JSP(dev_priv)) {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
> tc_hotplug_trigger = 0;
> } else if (HAS_PCH_MCC(dev_priv)) {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> @@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> INTEL_PCH_TYPE(dev_priv));
>
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
> tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
> }
> @@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> ddi_hotplug_trigger, dig_hotplug_reg,
> dev_priv->hotplug.pch_hpd,
> - icp_ddi_port_hotplug_long_detect);
> + ddi_port_hotplug_long_detect);
> }
>
> if (tc_hotplug_trigger) {
> @@ -3147,6 +3181,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> TGP_DDI_HPD_ENABLE_MASK, 0);
> }
>
> +static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +{
> + icp_hpd_irq_setup(dev_priv,
> + SDE_DDI_MASK_DG1, 0,
> + DG1_DDI_HPD_ENABLE_MASK, 0);
> +}
> +
> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> u32 hotplug;
> @@ -3535,7 +3576,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
> I915_WRITE(SDEIMR, ~mask);
>
> - if (HAS_PCH_TGP(dev_priv))
> + if (HAS_PCH_DG1(dev_priv))
> + icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0);
> + else if (HAS_PCH_TGP(dev_priv))
> icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
> TGP_TC_HPD_ENABLE_MASK);
> else if (HAS_PCH_JSP(dev_priv))
> @@ -4051,7 +4094,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> if (I915_HAS_HOTPLUG(dev_priv))
> dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> } else {
> - if (HAS_PCH_JSP(dev_priv))
> + if (HAS_PCH_DG1(dev_priv))
> + dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
> + else if (HAS_PCH_JSP(dev_priv))
> dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
> else if (HAS_PCH_MCC(dev_priv))
> dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6649aeca25d72..13a989f5e8dd3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8168,6 +8168,10 @@ enum {
> SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
> SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
> SDE_TC_HOTPLUG_ICP(PORT_TC1))
> +#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
> + SDE_DDI_HOTPLUG_ICP(PORT_C) | \
> + SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> + SDE_DDI_HOTPLUG_ICP(PORT_A))
>
> #define SDEISR _MMIO(0xc4000)
> #define SDEIMR _MMIO(0xc4004)
> @@ -8367,6 +8371,10 @@ enum {
> #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
> ICP_TC_HPD_ENABLE(PORT_TC5) | \
> ICP_TC_HPD_ENABLE_MASK)
> +#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>
> #define _PCH_DPLL_A 0xc6014
> #define _PCH_DPLL_B 0xc6018
> --
> 2.26.2
>
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