[Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1409371443

[Matt Atwood]

On Mon, Jun 01, 2020 at 06:49:10PM -0700, Aditya Swarup wrote:
> Set GMBUS0 Pin Pair Select to 1 at boot and each FLR exit.
> Return GMBUS0 Pin Pair Select to 1 after GMBUS transactions are done.
> 
> Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Piotr Piórkowski <piotr.piorkowski at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Jose Souza <jose.souza at intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h            |  2 ++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index a8d119b6b45c..8dd5aa025c3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -139,11 +139,19 @@ to_intel_gmbus(struct i2c_adapter *i2c)
>  	return container_of(i2c, struct intel_gmbus, adapter);
>  }
>  
> +static void gmbus0_wa_reset(struct drm_i915_private *dev_priv)
> +{
> +	intel_de_write(dev_priv, GMBUS0, 0 | GMBUS_PIN_PAIR_1);
or'ing with 0 doesnt make sense here, did you mean something else?
> +}
> +
>  void
>  intel_gmbus_reset(struct drm_i915_private *dev_priv)
>  {
>  	intel_de_write(dev_priv, GMBUS0, 0);
>  	intel_de_write(dev_priv, GMBUS4, 0);
> +	/* Wa_1409371443: tgl[a0] */
> +	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> +		gmbus0_wa_reset(dev_priv);
>  }
>  
>  static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
> @@ -299,6 +307,10 @@ intel_gpio_post_xfer(struct i2c_adapter *adapter)
>  
>  	if (IS_PINEVIEW(dev_priv))
>  		pnv_gmbus_clock_gating(dev_priv, true);
> +
> +	/* Wa_1409371443: tgl[a0] */
> +	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> +		gmbus0_wa_reset(dev_priv);
>  }
>  
>  static void
> @@ -955,4 +967,8 @@ void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
>  		bus = &dev_priv->gmbus[pin];
>  		i2c_del_adapter(&bus->adapter);
>  	}
> +
> +	/* Wa_1409371443: tgl[a0] */
> +	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> +		gmbus0_wa_reset(dev_priv);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 578cfe11cbb9..a1640476cefb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3337,6 +3337,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define   GMBUS_RATE_1MHZ	(3 << 8) /* reserved on Pineview */
>  #define   GMBUS_HOLD_EXT	(1 << 7) /* 300ns hold time, rsvd on Pineview */
>  #define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
> +#define   GMBUS_PIN_PAIR_MASK	REG_GENMASK(4, 0)
> +#define   GMBUS_PIN_PAIR_1	REG_FIELD_PREP(GMBUS_PIN_PAIR_MASK, 1)
>  
>  #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
>  #define   GMBUS_SW_CLR_INT	(1 << 31)
> -- 
> 2.26.2
> 
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