[Intel-gfx] [PATCH 1/2] drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock

[Almahallawy, Khaled]

On Mon, 2020-06-29 at 21:58 +0300, Imre Deak wrote:
> When the reference clock is 38.4MHz, using the current TBT PLL
> fractional divider value results in a slightly off TBT link
> frequency.
> This causes an endless loop of link training success followed by a
> bad
> link signaling and retraining at least on a ThinkPad 40AC TBT
> dock.  The
> workaround provided by the HW team is to divide the fractional
> divider
> value by two. This fixed the link training problem on the ThinkPad
> dock.
> 
> The same workaround is needed on some EHL platforms and for combo PHY
> PLLs, these will be addressed in a follow-up.
> 
> Bspec: 49204
> 
> References: HSDES#22010772725
> References: HSDES#14011861142
> Reported-and-tested-by: Khaled Almahallawy <
> khaled.almahallawy at intel.com>
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index b45185b80bec..f585053d02d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2937,6 +2937,12 @@ static const struct skl_wrpll_params
> tgl_tbt_pll_24MHz_values = {
>  	.pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
>  };
>  
> +static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = {
> +	.dco_integer = 0x54, .dco_fraction = 0x1800,
> +	/* the following params are unused */
> +	.pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
> +};
> +
>  static bool icl_calc_dp_combo_pll(struct intel_crtc_state
> *crtc_state,
>  				  struct skl_wrpll_params *pll_params)
>  {
> @@ -2970,12 +2976,14 @@ static bool icl_calc_tbt_pll(struct
> intel_crtc_state *crtc_state,
>  			MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
>  			/* fall-through */
>  		case 19200:
> -		case 38400:
>  			*pll_params = tgl_tbt_pll_19_2MHz_values;
>  			break;
>  		case 24000:
>  			*pll_params = tgl_tbt_pll_24MHz_values;
>  			break;
> +		case 38400:
> +			*pll_params = tgl_tbt_pll_38_4MHz_values;
> +			break;
>  		}
>  	} else {
>  		switch (dev_priv->dpll.ref_clks.nssc) {

Reviewed-by: Khaled Almahallawy <khaled.almahallawy at intel.com>