[Intel-gfx] [PATCH 1/4] drm/i915: Don't check uv_wm in skl_plane_wm_equals()

Souza, Jose jose.souza at intel.com
Wed Mar 4 00:14:59 UTC 2020


On Fri, 2020-02-28 at 22:35 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> The hardware never sees the uv_wm values (apart from
> uv_wm.min_ddb_alloc affecting the ddb allocation). Thus there
> is no point in comparing uv_wm to determine if we need to
> reprogram the watermark registers. So let's check only the
> rgb/y watermark in skl_plane_wm_equals(). But let's leave
> a comment behind so that the next person reading this doesn't
> get as confused as I did when I added this check.
> 
> If the ddb allocation ends up changing due to uv_wm
> skl_ddb_add_affected_planes() takes care of adding the plane
> to the state.
> 
> TODO: we should perhaps just eliminate uv_wm from the state
> and simply track the min_ddb_alloc for uv instead.
> 

Reviewed-by: José Roberto de Souza <jose.souza at intel.com>

> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 345429e5ad45..39299811b650 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5400,8 +5400,12 @@ static bool skl_plane_wm_equals(struct
> drm_i915_private *dev_priv,
>  	int level, max_level = ilk_wm_max_level(dev_priv);
>  
>  	for (level = 0; level <= max_level; level++) {
> -		if (!skl_wm_level_equals(&wm1->wm[level], &wm2-
> >wm[level]) ||
> -		    !skl_wm_level_equals(&wm1->uv_wm[level], &wm2-
> >uv_wm[level]))
> +		/*
> +		 * We don't check uv_wm as the hardware doesn't
> actually
> +		 * use it. It only gets used for calculating the
> required
> +		 * ddb allocation.
> +		 */
> +		if (!skl_wm_level_equals(&wm1->wm[level], &wm2-
> >wm[level]))
>  			return false;
>  	}
>  


More information about the Intel-gfx mailing list