[Intel-gfx] [PATCH 3/7] drm/i915: Add Wa_1604278689:icl,ehl

[Matt Roper]

On Tue, Mar 10, 2020 at 04:37:52PM +0000, Chris Wilson wrote:
> Quoting Matt Roper (2020-03-10 00:49:07)
> > The bspec description for this workaround tells us to program
> > 0xFFFF_FFFF into both FBC_RT_BASE_ADDR_REGISTER_* registers, but we've
> > previously found that this leads to failures in CI.  Our suspicion is
> > that the failures are caused by this valid turning on the "address valid
> > bit" even though we're intentionally supplying an invalid address.
> > Experimentation has shown that setting all bits _except_ for the
> > RT_VALID bit seems to avoid these failures.
> > 
> > v2:
> >  - Mask off the RT_VALID bit.  Experimentation with CI trybot indicates
> >    that this is necessary to avoid reset failures on BCS.
> 
> What reset failures?

It was back in August, so I think the logs have expired from CI now:

https://patchwork.freedesktop.org/series/65276/#rev1


Matt

>  
> > Bspec: 11388
> > Bspec: 33451
> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> >  drivers/gpu/drm/i915/i915_reg.h             | 1 +
> >  2 files changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 3e352e2a5b79..1cf931dde0ca 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -575,6 +575,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >         /* allow headerless messages for preemptible GPGPU context */
> >         WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
> >                           GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
> > +
> > +       /* Wa_1604278689:icl,ehl */
> > +       wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
> > +                          0, /* write-only register; skip validation */
> > +                          0xFFFFFFFF);
> > +       wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
> 
> Disable first.
> -Chris

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795